/*
* Copyright (C) 2016 Protonic Holland
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arm/imx6ul.dtsi>
#include <dt-bindings/gpio/gpio.h>
/ {
chosen {
stdout-path = &uart1;
environment@0 {
compatible = "barebox,environment";
device-path = &flash, "partname:env";
};
};
memory {
reg = <0x80000000 0x10000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p2v: 3p2-regulator {
compatible = "regulator-fixed";
regulator-name = "regulator-3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_1p35v: 1p35-regulator {
compatible = "regulator-fixed";
regulator-name = "regulator-1P35V";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
};
leds: leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
debug {
label = "debug0";
gpios = <&gpio4 16 0>;
linux,default-trigger = "heartbeat";
};
};
};
&usbotg1 {
dr_mode = "host";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_3p2v>;
wakeup-source;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
non-removable;
status = "okay";
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: w25q64fv@0 {
compatible = "winbond,w25q64", "jedec,spi-nor";
spi-max-frequency = <20000000>;
m25p,fast-read;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x0 0x60000>; /* 384 Kb */
};
partition@60000 {
label = "env";
reg = <0x60000 0x10000>; /* 64 Kb */
};
partition@70000 {
label = "dtb";
reg = <0x70000 0x10000>; /* 64 Kb */
};
partition@80000 {
label = "kernel";
reg = <0x80000 0x780000>; /* 7680 Kb */
};
};
};
&ecspi2 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
/* RFID chip */
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
rtc: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
tmp103: tmp103@70 {
compatible = "ti,tmp103", "tmp103";
reg = <0x70>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1 &pinctrl_ethphy0_rst>;
phy-mode = "rmii";
phy-handle = <ðphy0>;
phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
phy-reset-duration = <11>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
prti6g {
pinctrl_hog: hoggrp {
fsl,pins = <
/* HW revision detect */
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 /* REV_ID2 */
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 /* REV_ID3 */
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BOARD_ID0 */
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 /* BOARD_ID1 */
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* BOARD_ID2 */
MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 /* BOARD_ID3 */
/* CAN diagnostics (nSMBALERT) */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0 /* SD1 CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_ethphy0_rst: ethphy-rstgrp-0 {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880 /* PHY RESET */
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 /* SR */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* TERM */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 /* nSMBALERT */
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* SR */
>;
};
};
};
