/*
* dtsi file for Hisilicon Hi6220 coresight
*
* Copyright (C) 2017 Hisilicon Ltd.
*
* Author: Pengcheng Li <lipengcheng8@huawei.com>
* Leo Yan <leo.yan@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*
*/
/ {
soc {
funnel@f6401000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xf6401000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
out-ports {
port {
soc_funnel_out: endpoint {
remote-endpoint =
<&etf_in>;
};
};
};
in-ports {
port {
soc_funnel_in: endpoint {
remote-endpoint =
<&acpu_funnel_out>;
};
};
};
};
etf@f6402000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0xf6402000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
in-ports {
port {
etf_in: endpoint {
remote-endpoint =
<&soc_funnel_out>;
};
};
};
out-ports {
port {
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
};
};
};
};
replicator {
compatible = "arm,coresight-replicator";
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
in-ports {
port {
replicator_in: endpoint {
remote-endpoint =
<&etf_out>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint =
<&etr_in>;
};
};
port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint =
<&tpiu_in>;
};
};
};
};
etr@f6404000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0xf6404000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
in-ports {
port {
etr_in: endpoint {
remote-endpoint =
<&replicator_out0>;
};
};
};
};
tpiu@f6405000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0 0xf6405000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
in-ports {
port {
tpiu_in: endpoint {
remote-endpoint =
<&replicator_out1>;
};
};
};
};
funnel@f6501000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xf6501000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
out-ports {
port {
acpu_funnel_out: endpoint {
remote-endpoint =
<&soc_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
acpu_funnel_in0: endpoint {
remote-endpoint =
<&etm0_out>;
};
};
port@1 {
reg = <1>;
acpu_funnel_in1: endpoint {
remote-endpoint =
<&etm1_out>;
};
};
port@2 {
reg = <2>;
acpu_funnel_in2: endpoint {
remote-endpoint =
<&etm2_out>;
};
};
port@3 {
reg = <3>;
acpu_funnel_in3: endpoint {
remote-endpoint =
<&etm3_out>;
};
};
port@4 {
reg = <4>;
acpu_funnel_in4: endpoint {
remote-endpoint =
<&etm4_out>;
};
};
port@5 {
reg = <5>;
acpu_funnel_in5: endpoint {
remote-endpoint =
<&etm5_out>;
};
};
port@6 {
reg = <6>;
acpu_funnel_in6: endpoint {
remote-endpoint =
<&etm6_out>;
};
};
port@7 {
reg = <7>;
acpu_funnel_in7: endpoint {
remote-endpoint =
<&etm7_out>;
};
};
};
};
etm@f659c000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf659c000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&acpu_funnel_in0>;
};
};
};
};
etm@f659d000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf659d000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu1>;
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&acpu_funnel_in1>;
};
};
};
};
etm@f659e000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf659e000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu2>;
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&acpu_funnel_in2>;
};
};
};
};
etm@f659f000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf659f000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu3>;
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&acpu_funnel_in3>;
};
};
};
};
etm@f65dc000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf65dc000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu4>;
out-ports {
port {
etm4_out: endpoint {
remote-endpoint =
<&acpu_funnel_in4>;
};
};
};
};
etm@f65dd000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf65dd000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu5>;
out-ports {
port {
etm5_out: endpoint {
remote-endpoint =
<&acpu_funnel_in5>;
};
};
};
};
etm@f65de000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf65de000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu6>;
out-ports {
port {
etm6_out: endpoint {
remote-endpoint =
<&acpu_funnel_in6>;
};
};
};
};
etm@f65df000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf65df000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu7>;
out-ports {
port {
etm7_out: endpoint {
remote-endpoint =
<&acpu_funnel_in7>;
};
};
};
};
};
};
