/dts-v1/;
#include <arm/imx6dl.dtsi>
#include "imx6dl.dtsi"
/ {
model = "ELTEC HiPerCam";
compatible = "eltec,hipercam-rev01", "fsl,imx6dl";
memory {
reg = <0x10000000 0x10000000>;
};
chosen {
stdout-path = &uart1;
environment {
compatible = "barebox,environment";
device-path = &environment_nor0;
};
};
};
&ecspi1 {
status = "okay";
fsl,spi-num-chipselects = <2>;
pinctrl-names = "default";
cs-gpios = <&gpio2 30 0 &gpio3 19 0>;
pinctrl-0 = <&pinctrl_ecspi1>;
norflash0: s25fl129p1@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "st,s25fl129p1";
spi-max-frequency = <20000000>;
reg = <0x0>;
partition@0 {
label = "barebox";
reg = <0x0 0xe0000>;
};
environment_nor0: partition@e0000 {
label = "bareboxenv";
reg = <0xe0000 0x20000>;
};
partition@100000 {
label = "persistent";
reg = <0x100000 0xf00000>;
};
};
norflash1: s25fl129p1@1 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "st,s25fl129p1";
spi-max-frequency = <20000000>;
reg = <0x1>;
partition@0 {
label = "Linux";
reg = <0x0 0x1000000>;
};
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&pcie {
status = "okay";
reset-gpio = <&gpio7 12 0x0>;
};
&usdhc3 {
bus-width = <0x4>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 1 0>;
no-1-8-v;
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x20>;
eeprom@52 {
compatible = "amtel,24c04";
reg = <0x52>;
pagesize = <0x10>;
};
pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x8>;
regulators {
sw1ab {
regulator-min-microvolt = <0x493e0>;
regulator-max-microvolt = <0x1c9c38>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <0x186a>;
};
sw1c {
regulator-min-microvolt = <0x493e0>;
regulator-max-microvolt = <0x1c9c38>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <0x186a>;
};
sw2 {
regulator-min-microvolt = <0xc3500>;
regulator-max-microvolt = <0x325aa0>;
regulator-boot-on;
regulator-always-on;
};
sw3a {
regulator-min-microvolt = <0x61a80>;
regulator-max-microvolt = <0x1e22d8>;
regulator-boot-on;
regulator-always-on;
};
sw3b {
regulator-min-microvolt = <0x61a80>;
regulator-max-microvolt = <0x1e22d8>;
regulator-boot-on;
regulator-always-on;
};
sw4 {
regulator-min-microvolt = <0xc3500>;
regulator-max-microvolt = <0x325aa0>;
};
swbst {
regulator-min-microvolt = <0x4c4b40>;
regulator-max-microvolt = <0x4e9530>;
};
vsnvs {
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0x2dc6c0>;
regulator-boot-on;
regulator-always-on;
};
vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1 {
regulator-min-microvolt = <0xc3500>;
regulator-max-microvolt = <0x17a6b0>;
};
vgen2 {
regulator-min-microvolt = <0xc3500>;
regulator-max-microvolt = <0x17a6b0>;
};
vgen3 {
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x325aa0>;
};
vgen4 {
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x325aa0>;
regulator-always-on;
};
vgen5 {
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x325aa0>;
regulator-always-on;
};
vgen6 {
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x325aa0>;
regulator-always-on;
};
};
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x1d>;
mt9p031@48 {
compatible = "aptina,mt9p031";
reg = <0x48>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cam>;
csi_id = <0x0>;
clocks = <&clks 201>;
clock-names = "csi_mclk";
rst-gpios = <&gpio5 22 0>;
data-enable-gpios = <&gpio5 20 0x0>;
mclk = <12000000>;
mclk_source = <0>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6dl-eltec-hipercam {
pinctrl_ecspi1: ecspi1 {
fsl,pins = <MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1
>;
};
pinctrl_i2c1: i2c1 {
fsl,pins = <MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2 {
fsl,pins = <MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3 {
fsl,pins = <MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pwm1: pwm1 {
fsl,pins = <MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1>;
};
pinctrl_uart1: uart1 {
fsl,pins = <MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3 {
fsl,pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_hog: hog {
fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x80000000
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
>;
};
pinctrl_cam: cam {
fsl,pins = <MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
>;
};
};
};
