ARM: socfpga: achilles: convert to PBL barebox
Previously the FPGA was configured externally on the Achilles. On newer versions this is changed and barebox has to configure the FPGA before the SDRAM can be used. If the FPGA is configured via JTAG or from an external memory, the *-bringup version can be used. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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arch/arm/boards/reflex-achilles/Makefile |
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arch/arm/boards/reflex-achilles/board.c 0 → 100644 |
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arch/arm/boards/reflex-achilles/lowlevel.c |
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images/Makefile.socfpga |
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