Due to a wrong rounding while calculating the clock divider the requested clock
of 25 MHz resulted into a 48 MHz clock. With this patch a clock frequency
below or equal the requested one will be set.
By using 'div' and 'rate' as vars, its also easier to check against the data
sheet.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>