clk: i.MX6qp: Fix location of the enfc_sel mux
On the i.MX6qp the enfc_sel mux is at bits 15-17, not on 16-17. Fix this. During clock tree initialization we reparented the enfc_sel to: clk_set_parent(clks[IMX6QDL_CLK_ENFC_SEL], clks[IMX6QDL_CLK_PLL2_PFD2_396M]); This resulted in a register setting 0b110 for the enfc_sel mux which is reserved. Apparently this reserved setting resulted in the enfc clock being driven from pll3_pfd3_454m. This means our enfc clock was the factor 454/396 too high. With b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK") we happened to disable pll3_pfd3_454m during init, so with this commit NAND stopped working entirely on i.MX6qp. Both issues are fixed with this patch Fixes: b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK") Fixes: 92fd61d12723 ("clk: i.MX6: Fix enfc_sel for i.MX6dqp") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> |
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drivers/clk/imx/clk-imx6.c |
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