ARM: pfla02: Set new ethernet phy tx timings
TX_CLK line is approx. 54mm longer than other TX lines which adds
a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add
a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by
setting GTX pad skew value to 11100
Also add a delay for the RX delay lines, needed for the Duallite variant.
 => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
1 parent 2863149 commit 4c65c20f107113b82bf0aae6072fbb2affb6d1f7
@Christian Hemp Christian Hemp authored on 8 Aug 2013
Sascha Hauer committed on 26 Mar 2014
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arch/arm/boards/phytec-phyflex-imx6/board.c