Read leveling delays are being specified as zero, so they are as good
as disabled and can be safely dropped.

Gate training delay is specified as 4/128 tCK for both data
slices. This setting, when applied to Data Byte 1, makes that slice
unusable* during POR startup which is somehow is mitigated by
double-reset hack in DCD.

Dropping gate training delays allows both VF610 Tower board and ZII
VF610 Dev board to sucessfully PoR-boot without the need for double
resetting of the DDRMC.

* The board fails to boot. When examined via JTAG in such a state
  only even bytes of DDR memory are functional.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>