Check if PLL2 PFD0 or PLL2 PFD2 is selected as clock source in
register CCM CBCMR->pre_periph_clk_sel or CCM CBCMR->pre_periph2_clk.
Don't reset the used PFDs to avoid system hang.

ported from https://github.com/Freescale/u-boot-fslc/
commit/9293d7fd502ce29302fadb8b4ccb9231ec0bcc66

Signed-off-by: Marc Ohlf <ohlf@mkt-sys.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>