clk: tegra: don't bug out on zero PLL postdiv
As the real value is 2^p a input value of 0 is
actually valid.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
1 parent d95bb6f commit 89b062b4308d84215306b042afd158a8e6ebe3af
@Lucas Stach Lucas Stach authored on 3 Jun 2014
Sascha Hauer committed on 5 Jun 2014
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drivers/clk/tegra/clk-pll.c