Although upstream U-Boot does not initialize this register in
vf610-twr code (it does so in code for Phytec's PCM052) multiple
revisions of VFxxx Controller Reference Manual state:

    5.2.6.1 DUMMY PADS (DDR/QuadSPI)

    There are two dummy pads that are useful for timing calibration of
    DDR. These pads are internal only, but there corresponding IOMUX
    register need to be programmed for correct operation of DDR. These
    registers are:

              * IOMUXC_DUMMY_DDRBYTE1 (0x400482DC)
              * IOMUXC_DUMMY_DDRBYTE2 (0x400482E0)

    DDR: Dummy pads for DDR must be configured before any DDR I/O
    transactions are done. These pads simulate the input delay of the
    I/O buffers from the DRAM devices and DDR configures the delays
    accordingly.

Although current DCD works as is, add writes for those registers for
the sake of completness.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>