Altera's SocFPGA Arria10 SoC uses a new image format, different from
the one used on CycloneV.  The formats are similar, with the header
matching up to the point where the version field is 1 instead of 0.
At that point the header fields diverge.  The CRC and checksum use is
the same between the two.

This patch extends socfpga_mkimage to support generating the new
format with a version command line option.  The default will be V0 for
CycloneV.

The new format is, IMHO, not as good as the previous one.  It requires
the start location be after the header, while the V0 format would
allow the start location to be before or after.  Barebox boot images
are designed to start from offset 0, which is before the header.  To
avoid modifying the common barebox start code specifically for
Arria10, I instead add a trampoline instruction after the V1 header to
jump to the real start location, wherever it might be.

Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>