Currently, both SDHC clock source is PLL3. We can raise clock
for SDHC driver by change source from PLL3 to PLL2.
Below, is debug ouputs with old and new settings.

Detection (PLL3):
set clock: wanted: 400000 got: 375000
Operation (PLL3):
set clock: wanted: 25000000 got: 18000000
Operation SD4.0 (PLL3):
set clock: wanted: 52000000 got: 27000000

Detection (PLL2):
set clock: wanted: 400000 got: 399639
Operation (PLL2):
set clock: wanted: 25000000 got: 23750000
Operation SD4.0 (PLL2):
set clock: wanted: 52000000 got: 41562500

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>