ARM: at91: add sama5d2 cache init
The L2 cache controller needs some initialization before use. Same goes
for the CAN SRAM, do so after the MMU setup.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
1 parent 6199e56 commit c0edbe48a4e00194cf4490b7c673e6f4a91d251f
@Ahmad Fatoum Ahmad Fatoum authored on 1 Jul 2020
Sascha Hauer committed on 11 Jul 2020
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arch/arm/mach-at91/Makefile
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arch/arm/mach-at91/sama5d2.c 0 → 100644