ARM: at91: add sama5d2 cache init
The L2 cache controller needs some initialization before use. Same goes for the CAN SRAM, do so after the MMU setup. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> |
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arch/arm/mach-at91/Makefile |
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arch/arm/mach-at91/sama5d2.c 0 → 100644 |
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