usb: dwc3: Toggle GCTL.CORESOFTRESET as a first step
Toggle GCTL.CORESOFTRESET before trying to access any of the block's
registers. Without this additional step, first read of DWC3_GHWPARAMS*
that follows results in assertion of GSTS.CSRTIMEOUT and IP block
stuck in a non-functional state.

Note that all above has only been observerd on i.MX8MQ (ZII Zest
board) for USB1 controller. USB2 doesn't seem to be affected by this.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
1 parent d696289 commit eb1e8358f49ed6d78b5395857767296934decd3b
@Andrey Smirnov Andrey Smirnov authored on 13 Mar 2019
Sascha Hauer committed on 18 Mar 2019
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drivers/usb/dwc3/core.c