Previous code ran the edb9302(a) boards with the PLL same settings as the
edb9301, at 166MHz core and 66MHz system bus clock. In difference to the edb9301
board the edb9302(a) is equipped with an EP9302 processor, which can be clocked
at higher rates than the EP9301. Therefore we can configure the edb9302(a) with
the same PLL settings as the other non-edb9301 boards, namely at 200MHz for
the core and 100MHz for the system bus clock.

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>