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History for barebox / arch / arm / mach-tegra / tegra_avp_init.c

2015-03-03	09c4b63 Browse files » tegra: avp_init: write DT address register earlier ... Otherwise the write would be skipped if we are already running on the main CPU cluster. In practice this means that a second stage barebox will reuse the DT of the first stage, instead of using it's own. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 2 Mar 2015 Sascha Hauer committed on 3 Mar 2015
2014-06-05	08f5fcb Browse files » tegra: hardcode entry address for main cluster ... I don't know why get_runtime_offset fails on T124 yet, but this is a safe workaround, with the nice side-effect of fixing second stage barebox loading. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 3 Jun 2014 Sascha Hauer committed on 5 Jun 2014
	8dc05ab Browse files » tegra: apply cluster switch logic to all SoCs >=T30 ... Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 3 Jun 2014 Sascha Hauer committed on 5 Jun 2014
	566fd49 Browse files » tegra: add Tegra124 PLL_X rate setup ... Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 3 Jun 2014 Sascha Hauer committed on 5 Jun 2014
	983f39f Browse files » tegra: change cpu internal reset layout for Tegra124 ... Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 3 Jun 2014 Sascha Hauer committed on 5 Jun 2014
	3d6fced Browse files » tegra: fix MESLECT clock enable ... Don't disable clk to unrelated devices in the process. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 3 Jun 2014 Sascha Hauer committed on 5 Jun 2014
	3e5f060 Browse files » tegra: power up additional partitions on Tegra124 ... Those 3 are needed to power CPU0 from the CPUG cluster. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 3 Jun 2014 Sascha Hauer committed on 5 Jun 2014
	3cc59d0 Browse files » tegra: disable IDDQ for PLL_X on Tegra124 ... This is an additional power down control. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 3 Jun 2014 Sascha Hauer committed on 5 Jun 2014
2014-05-08	acbecd1 Browse files » ARM: tegra30: slow down CPU to 600 MHz ... It's not safe to ramp up the CPU clock speed to 1,4 GHz on all T30 SKUs, as this may result in failure to start the kernel properly. Start CPU at 600 MHz, which is safe even for the slowest SKUs. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 7 May 2014 Sascha Hauer committed on 8 May 2014
2014-04-23	0fe9761 Browse files » tegra: source MSELECT clock from CLK_M ... We need to reprogram PLL_P at a later time, so we have to make sure MSELECT is able to operate correctly when we stop PLL_P. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 13 Apr 2014 Sascha Hauer committed on 23 Apr 2014
2014-02-27	df1d532 Browse files » tegra: add Tegra3 startup ... Sets up MSELECT to let main CPUs talk to peripheral devices and starts high performance A9 CPU cluster. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 17 Feb 2014 Sascha Hauer committed on 27 Feb 2014
2014-02-27	880869e Browse files » tegra: set AHB clock rate early ... Avoids glitches in later starup phases. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 17 Feb 2014 Sascha Hauer committed on 27 Feb 2014
2014-02-19	af155f7 Browse files » tegra: add lowlevel delay function ... For proper startup we need to give clocks and IO signals some time to stabilize. Tegra2 got away without them, but Tegra3 seems to be a bit pickier. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 17 Feb 2014 Sascha Hauer committed on 19 Feb 2014
2013-12-04	c50a171 Browse files » tegra: fix fallout from relocatable code changes in PLLX init ... Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 3 Dec 2013 Sascha Hauer committed on 4 Dec 2013
2013-10-02	f93b5f8 Browse files » tegra: switch to multi image ... To keep things clean I removed all support for the old way to build images. There is now a single tegra_v7 defconfig which builds both supported Tegra boards as images. The new image generation also paves the way for integration of the tegra-cbootimage tool to produce directly flashable images. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Sep 2013 Sascha Hauer committed on 2 Oct 2013
	c05a80c Browse files » tegra: fix PBL build ... Drop useless BUG(), we are too early for them to be of any use. Make sure we build the AVP code as ARMv4 even in PBL case. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Sep 2013 Sascha Hauer committed on 2 Oct 2013
	0256852 Browse files » tegra: start maincomplex execution at correct offset ... Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 29 Sep 2013 Sascha Hauer committed on 2 Oct 2013
2013-07-02	acc791f Browse files » tegra: deduplicate clk defines ... Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 30 Jun 2013 Sascha Hauer committed on 2 Jul 2013
2013-04-14	789c55b Browse files » tegra: add common lowlevel startup ... All Tegra20 boards have a common startup sequence. Also there is an agreement on how to find out about the installed amount of RAM and other information needed by early startup. So as there is really no need to do any lowlevel stuff per board, we can just do it at the ARCH level. This also enables the first stage loading of barebox by detecting the currently running CPU and booting the main CPU cluster if neccesary. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 12 Apr 2013 Sascha Hauer committed on 14 Apr 2013