Unlike the Linux kernel, barebox does not have a dedicated heap for
storing modules. Therefore, if the system memory configuration places
the general heap further away than can be reached by a 'bl' instruction
(24 bits of address, or 16 MiB), then the module relocations will fail
due to being out of range.

Allocate PLTs when loading modules so that jumps and calls whose
targets are too far away for their relative offsets to be encoded
in the instructions themselves can be bounced via veneers in the
module's PLT. The modules will use slightly more memory, but after
rounding up to page size, the actual memory footprint is usually
the same.

Adoption of Linux commits:

66e94ba3c8ea ARM: kernel: avoid brute force search on PLT generation
1031a7e674d1 ARM: kernel: sort relocation sections before allocating PLTs
05123fef0982 ARM: kernel: allocate PLT entries only for external symbols
35fa91eed817 ARM: kernel: merge core and init PLTs
7d485f647c1f ARM: 8220/1: allow modules outside of bl range

Signed-off-by: David Dgien <dgienda125@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Other arch-specific features are exposed in Kconfig too, so do here
likewise.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The optimized find bit functions are only implemented for 32 bit and are
not built on aarch64 systems. Therefore, for example bootchooser cannot
be build for aarch64.

Select the generic find_bit implementations on aarch64.

As the decision, if lib64 or lib32 is build or not, directly depends on
CPU_V8, the generic implementation also should be used if CPU_V8 is
selected.

Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

AArch64 implements all of the DMA API functions, so it should select
HAS_DMA to allow building drivers that depend on that.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PBL is another feature, which needs some love to work on ARM64.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

We don't yet have an implementation for those two features on ARM64, so move
them to a place where they are only selected for a 32bit barebox.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The current ARM64 lowlevel code needs the exception vector to set
up all the ELs. Select ARM_EXCEPTIONS to make sure this is always
present.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add the pxa3xx architecture, for pxa300, pxa310 and pxa320 SoCs.
This includes :
 - the registers
 - the cpu type
 - the reset source handling
 - a minimal set of clocks
 - pin control definitions
   In this last case, the big mfp-pxaxxx.h files were dropped, forcing
   board developers to use MFP_LPM_* macros cunningly.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

CPU_ARM946E is selected by boards, so letting it depend on !MMU
leads to broken dependencies. Let MMU depend on !CPU_ARM946E instead.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM946E-S is used in the DIGIC family SoCs.

ARM946E-S core supports ARMv5TE and has Cache & MPU.
Linux kernel uses ARMv4 MPU cache routines for ARM946E-S core.
E.g. see linux.git/boot/compressed/head.S:

    .word   0x41009400              @ ARM94x
    .word   0xff00ff00
    W(b)    __armv4_mpu_cache_on
    W(b)    __armv4_mpu_cache_off
    W(b)    __armv4_mpu_cache_flush

So select CPU_32v4T for ARM946E-S despite of ARMv5TE support.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The Kirkwood Marvell SoC uses a Marvell-specific implementation of an
ARMv5TE compatible ARM core, the Feroceon. This patch introduces a
Kconfig option that allows to select this CPU type.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This patch provides a global cleanup barebox Kconfig files. This includes
replacing spaces to tabs, formatting in accordance format, removing
extraneous lines and spaces. No functional changes.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Carlo Caione <carlo.caione@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The core support was brought by Marc and Sascha.
The cache choice was fixed by Luotao Fu.
Some gpio and devices addons were provided by Robert.

Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

l2x0 cache support does not work without MMU, so depend
on it in Kconfig.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Currently implemented only in "bootz".

Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>