On i.MX6ul(l) (Cortex A7) We have to set the SMP bit before
enabling the caches, otherwise they won't work. Add a SoC specific
lowlevel_init function to be called by the i.MX6ul(l) boards.

Since this is a quirk of the Cortex A7 core we put the functionality
into a separate function to be reused by other Cortex A7 cores.

Change existing i.MX6ul(l) boards to use the new initialisation
function. It seems this is only needed when booting from USB,
in other boot modes the ROM will already have done the initialisation.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This adds support for the i.MX6UL Technexion Pico Hobbit. The board
comes with different amounts of RAM. We create one image for the 256MB
and one for the 512MB variant.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
   ---
   v1 -> v2: - removed already prepared clock setup
   v2 -> v3: - added phy-reset-post-delay as the support is now available

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>