On i.MX6ul(l) (Cortex A7) We have to set the SMP bit before
enabling the caches, otherwise they won't work. Add a SoC specific
lowlevel_init function to be called by the i.MX6ul(l) boards.

Since this is a quirk of the Cortex A7 core we put the functionality
into a separate function to be reused by other Cortex A7 cores.

Change existing i.MX6ul(l) boards to use the new initialisation
function. It seems this is only needed when booting from USB,
in other boot modes the ROM will already have done the initialisation.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

To avoid the code duplication between the static inline C
function and the assembly macro.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This adds a new function __barebox_arm_head() which defines an
the regular barebox ARM header, but which jumps to the end of
the function so that this can be embedded into another function.
barebox_arm_head() now just uses it and jumps to barebox_arm_reset_vector
just like it did before.

This makes it possible to define board specific entry points.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

On ARMv7 the intention is to disable the alignment trap to be able to
use hardware assisted unaligned load/stores. Fix the init to do the
right thing.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This adds 32bytes of space behind the image header (exception table
+ barebox magic) for board/SoC specific use. This can be used for
example to embed some extra information in a flashed image.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

reset is confusing with the cpu reset and impossible to grep

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

We allow unaligned accesses on ARMv6 onwards, make sure the CR_A
flag is cleared so that unaligned accesses do not trap.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

On some SoCs (for example AM35xx), the ROM bootloader passes useful
information in r0 when jumping to barebox.

To avoid overwriting this in the generic reset code, we introduce
common_reset as a C function and as an assembler macro. This is then
called form the reset entry point (either in common or in board code).

This patch is based on code by Sascha Hauer <s.hauer@pengutronix.de>.

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This is needed by at91 to specify the size of the binary to load from the
bootrom when booting for non nor flash.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This shrinks the resulting binary size by ~25%. Exceptions
are still handled in arm mode, so we have to explicitely
put .arm directives into the exception code. Thumb-2 mode
has been tested on i.MX51 Babbage board.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Traditionally U-Boot and barebox have the exception vectors at
the start of the binary. There is no real reason in doing so,
because in the majority of cases this data will not be at 0x0
where it could be used as vectors directly anyway.
This patch puts the vectors into a separate linker section and
defines an head function which is placed at the start of the
image instead. Putting this in a separate function also has
the advantage that it can be placed at the start of images
which require an additional header like several Freescale i.MX
images. As the head function contains the barebox arm magic
those images can now also be detected as barebox images.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>