PCM-060 modules only have one-bank RAMs populated, which allows us to
find out the populated RAM size at run-time.

Therefore, a new entry point was create 'PHYTEC_ENTRY_UNIFIED_MLO'. This
creates a MLO for all modules of one family and all existing PCM-060
MLOs were replaced with this new entry point. To provide backward
compatibility for older modules, these were not affected.

In the first step generic RAM timings for the module family get loaded,
because RAM accesses are only possible with an initialized controller.
After that, the RAM size will be calculated and the RAM controller gets
reinitialized with the correct RAM timings.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add a new device tree for phyCORE SOMs with EMMC enabled and NAND
disabled.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Starting with PCM-062, NAND isn't the main non-volatile memory for the
AM335x. Because that, NAND has be disabled in the SOM dtsi file and will
be enabled in a specific NAND SOM file.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This machine was a prototype and was never shipped to customers.

Since it has no dependencies to any image, it can be removed.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add new RAM Timings for phyCORE R2 with MT41K512M16HA-125IT
1024MB mounted.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Use ARM_USE_COMPRESSED_DTB for all AM335x based board,
to reduce the image size even more.

Saves about 9kB in MLO image and 20kB in barebox image.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add RAM timings for phyCORE-AM335x-R2 256MB RAM.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add RAM Timings for new phyCORE-AM335x-R2 SoM with
512MB (MT41K256M16TW107IT).

Signed-off-by: Arnd Beuscher <a.beuscher@phytec.de>
Sigend-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Setup the plls with Master Osc. clock speed from the SYSBOOT
Configuration Pin.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add support for all possible combinations of phyFLEX-AM335x modules.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add support for all possible combinations of phyCORE-AM335x
modules.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Added support for IM8G16D3FBBG15EI 1024MiB RAM on one chip.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add support for the phyCARD SOM.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The main idea behind this patch is to avoid redundant board code.
Because of the module similarities of all am335x based phytec boards, we can
merge its code.
The phytec-som-am335x merges the code of all am335x based phytec SOMs.
So we will have only one "board" in the barebox for phyCORE, phyFLEX.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>