ARM: Add PSCI support ...

This patch contains the barebox implementation for the ARM
"Power State Coordination Interface" (PSCI).

The interface is aimed at the generalization of code in the following
power management scenarios:
* Core idle management.
* Dynamic addition and removal of cores, and secondary core boot.
* big.LITTLE migration.
* System shutdown and reset.

In practice, all that's currently implemented is a way to enable the
secondary core one some SoCs.

With PSCI the Kernel is either started in nonsecure or in Hypervisor
mode and PSCI is used to apply power to the secondary cores.

The start mode is passed in the global.bootm.secure_state variable. This
enum can contain "secure" (Kernel is started in secure mode, means no
PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available)
or "hyp" (Kernel is started in hyp mode, meaning it can support
virtualization).

We currently only support putting the secure monitor code into SDRAM,
which means we always steal some amount of memory from the Kernel.
To keep things simple for now we simply keep the whole barebox binary in
memory

The PSCI support has been tested on i.MX7 only so far. The only
supported operations are CPU_ON and CPU_OFF.

The PSCI and secure monitor code is based on the corresponding U-Boot
code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add smc call support ...

Taken from the Kernel: A wrapper to make a smc call from C.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm64: include correct setupc file in ARM64 PBL ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: cpu: add basic arm64 mmu support ...

This commit adds basic mmu support, ie:
        - DMA cache handling is not supported
        - Remapping memory region also

The current mmu setting is:
        - 4KB granularity
        - 3 level lookup (skipping L0)
        - 33 bits per VA

This is based on coreboot and u-boot mmu configuration.

Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: cpu: add arm64 specific code ...

This patch adds arm64 specific codes, which are:
	- exception support
	- cache support
	- rework Makefile to support arm64

Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Fix exception table setup in MMU-less mode ...

Add code necessary for correct initialization of exception vector
table when MMU is disabled.

Note: Only ARMv7 support is implemented

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm/cpu: Avoid multiple definitions of barebox_arm_entry ...

All versions of barebox_arm_entry (in uncompress.c, start.c and
start-pbl.c) appear to be doing exacty the same thing. So move the
definition into a separate file and use IS_ENABLED macro to avoid
re-definition.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Pass armv7-a AFLAGS to cache-v7 ...

The cache-v7 code uses assembler instructions which do not
exist on before v7, so explicitely pass armv7-a to this file
to make the compiler happy.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Make multi images startup process simpler ...

The multi image startup process used to have three binaries involved:
- The lowlevel board code to initialize SDRAM
- the uncompressor
- the regular (compressed) barebox binary
Drop the uncompressor and put the uncompress code into the lowlevel
board code binary. This makes the startup process easier.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: invalidate caches thoroughly ...

The data caches should be invalided once during startup. This should
also be done when we do not have the MMU enabled in barebox because
the Kernel does not invalidate the caches during start.

To make this sure this patch enables the arm_early_mmu_cache_invalidate
function even if MMU support is disabled. Additionally this patch adds
calls to arm_early_mmu_cache_invalidate in start.c and uncompress.c.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Create an assembly arm_cpu_lowlevel_init function ...

To avoid the code duplication between the static inline C
function and the assembly macro.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add multi images support ...

This adds the make infrastructure to build multiple SoC or
board specific images from a single barebox binary.

The basic idea is that we no longer have a single pbl, but instead
multiple pbls, one per image if necessary. Each pbl is defined
by its entry function so that each pbl can do exactly what a given
board needs. Additionally the pbls together with a self extracting
barebox binary can be encapsulated in specific image formats.

squashed in build fixes from Lucas Stach for make version >= 3.82:

Split Multimage Makefile rule in explicit and implicit parts

Fixes build with make version >=3.82

Frome the make 3.82 NEWS file:
* WARNING: Backward-incompatibility!
  In previous versions of make it was acceptable to list one or more explicit
  targets followed by one or more pattern targets in the same rule and it
  worked "as expected".  However, this was not documented as acceptable and if
  you listed any explicit targets AFTER the pattern targets, the entire rule
  would be mis-parsed.  This release removes this ability completely: make
  will generate an error message if you mix explicit and pattern targets in
  the same rule.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Lucas Stach <dev@lynxeye.de>

ARM: Allow to pass a devicetree via boarddata ...

Addionally to having a builtin DTB provide the possibility for
the board to provide a dtb via boarddata.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/relocate' ...

Conflicts:
	arch/arm/lib/barebox.lds.S

ARM: Initial dts support ...

- Add rules to generate dtb files in arch/arm/dts/
- add an initcall which unflattens and probes the internal devicetree
- Add skeleton devicetree

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add relocatable binary support ...

For making the same binary executable on different SoCs which have
different DRAM addresses we have to be independent of the compile
time link address.

This patch adds relocatable binary support for the ARM architecture.
With this two new functions are available. relocate_to_current_adr
will fixup the binary to continue executing from the current position.
relocate_to_adr will copy the binary to a given address, fixup the
binary and continue executing from there.

For the PBL and the real image relocatable support can be enabled
independently. This is done to (hopefully) better cope with setups
where the PBL runs from SRAM or ROM and the real binary does not.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Factor out early mmu code ...

Move early mmu code to a separate file so that it can be
used from the pbl and the regular image. Disabling the mmu
can be dropped since the regular mmu code is now able to
pickup an enabled mmu.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/arm-start' into for-next/arm

ARM: Support multiple ARM architectures ...

The different ARM architectures need different cache functions. This
patch makes them selectable during runtime.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: add assembly function for setting up C environment ...

Sometimes Assembler beats C. In this case a small assembler
function called without parameters can:

- copy a binary to its link address
- clear the bss
- return to the same position in the copied binary

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: give boards control of the reset entry point ...

On some SoCs (for example AM35xx), the ROM bootloader passes useful
information in r0 when jumping to barebox.

To avoid overwriting this in the generic reset code, we introduce
common_reset as a C function and as an assembler macro. This is then
called form the reset entry point (either in common or in board code).

This patch is based on code by Sascha Hauer <s.hauer@pengutronix.de>.

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM pbl: enable MMU during decompression ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add pre-bootloader (pbl) image support ...

This allows for creating a pre-bootloader binary for
 - nand boot
 - mmc boot
 - compressed image

The pbl will be incharge of the lowlevel init if needed.
The barebox will skip it.

Import string functions from linux 3.4 (arch/arm/boot/compressed/string.c) and
implement a dummy panic.

For now on introduce dummy zbarebox* targets and c code that will contain later
the decompressor. This only implemeted on ARM.

This patch is based on Sascha Hauer <s.hauer@pengutronix.de>
Add compressed image support patch

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

mmuinfo: add a command do display the result of virtual to physical translation ...

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: make exception handling optional ...

On several boards without MMU support the vectors cannot be mapped
to 0x0 and exception support is nonfunctional anyway, so make this
configurable.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: reimplement startup code in C ...

Lets translate the startup code to a language we all understand better.
Tested on pcm038 (arm v5) and pcm043 (arm v6).

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

add l2x0 cache support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

armv5: use proper cache flush function ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm/cpu/Makefile: cleanup: proper indention ...

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

Use cache functions from kernel ...

These cache functions have been extracted from
arch/arm/boot/compressed/head.S. The old code only worked
properly on ARMv4. Tested on ARMv4, ARMv5, ARMv6 hardware.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>