ARM i.MX: add SoC type detection for i.MX6SL ...

The i.MX6 series SoC type is determined by barebox by examining the
USB_ANALOG_DIGPROG aka IMX6_ANATOP_SI_REV register. This register is located
at a common offset for all mx6 SoC - except for i.MX6SL where a different
offset is used. This creates a dilemma while distinguishing the mx6sl from
non-mx6sl SOC since the SoC type identification register location is type
specific itself.

Access to undocumented and probably invalid or unpredictable registers should
be avoided as possible. For the mx6sl detection an access to the general
USB_ANALOG_DIGPROG @0x260 cannot be avoided when running on mx6sl. This
register contained the value 0x00014009 for different mx6sl Rev. 1.2 based
e-book readers using MCIMX6L7DVN10AB and MCIMX6L8DVN10AB SoC. This
implementation assumes the value of MAJOR_UPPER (here 0x01) to be smaller
than the smallest non-6sl MAJOR_UPPER (0x61 for mx6s).

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/imx'

ARM: i.MX: beginning i.MX6ul support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: Register imx6_fixup_cpus() for MX6Q+ as well ...

Register imx6_fixup_cpus() for MX6Q+ as well as for MX6Q and MX6DL.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: Introduce imx6_cpu_revision() ...

Factor out CPU revision identification code from imx6_init() into a
standalone inline function (similar to imx6_cpu_type()), so that it
would be possible to use that functionality in PBL code.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6: remove duplicate clock initialization ...

These registers are already set by imx6_ccm_probe (in clk-imx6.c) during
core_initcall, while imx6_init_lowlevel is only called during
postcore_initcall via imx_init in imx.c.

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6qp: set NoC regulator to bypass ...

The NoC regulator only passes the QoS signals through if it is
in bypass mode. This is a safe setting to give the IPU priority
over other requests. The kernel may change it to some other setting
once it knows the bandwidth requirements of the use-case.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL ...

SX and SL variants only include the PXP and have no IPU, so
skip any IPU related QoS setup.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: split out IPU QoS setup ...

Split into separate function and only call it after the chip type
and revision is known.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX53: do not pass base address to imx*_boot_save_loc ...

The functions can determine the necessary base addresses
themselves since they are SoC specific anyway.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: reset PLL2's PFD2 on i.MX6D ...

The check for is_imx6q was introduced initially in

	f1f6d76370b3 ("ARM: i.MX6: correct work flow of PFDs from uboot-sources")

to differentiate between i.MX6DL+i.MX6SL and i.MX6Q. The i.MX6D must be
handled like the latter, so drop the check. i.MX6DL+i.MX6SL can be
ignored here since since

	a66596282413 ("imx6: lowlevel_init: Fix workaround for new i.MX6s chips")

the PFD handling is only done for i.MX6DQ.

Update the comment to be not only logically correct but also helpful.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX6: PL310: Adjust settings for performance ...

According to commit f6b6f3c from
git://git.freescale.com/imx/uboot-imx.git:

	Also set Prefetch offset to 15, since it improves
	memcpy performance by 35%. Don't enable Incr double
	Linefill enable since it adversely affects memcpy
	performance by about 32MB/s and reads by 90MB/s. Tested
	with 4K to 16MB sized src and dst aligned buffer.

This commit ports those chagnes from U-Boot.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX6: Apply PL310 errata base on PL310's revision ...

I.MX6Q Plus parts have r3p2 revision of PL310 so double linefill
errata no longer applies for all of the i.MX6Q SoCs. Change the code to
use PL310's revision inforation to determine if workaround needs to be
applied.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

L2x0: i.MX6: Replace magic numbers with constants ...

Use constants instead of magic numbers for PL301 registers bits in
imx6_mmu_init()

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: Add revision detection for i.MX6D/Q Plus ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/imx'

ARM: imx6: add OF fixup to delete nonexistent CPU cores ...

Make sure that the DT passed to Linux reflects the actual number of CPU
cores present in the system by reading the SCU configuration. As both
the Q and DL variants of the MX6 have versions with cores fused away,
but the DTs have the maximum number of cores specified, this just deletes
any nonexistent CPU core nodes.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: set shared attribute override bit in PL310 ...

In order to make the system compliant to the ARMv7 ARM RevC clarifications
regarding conflicting memory aliases the shared override bit needs to be
set. This needs to be done in the bootloader, as the kernel will not apply
any modifications to the AUX_CTRL register by default, as it is a secure only
register.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: use l2x0 header for register definitions ...

Instead of using a redundant definition. This makes things a bit cleaner
and also avoids to introduce another private define in the next patch.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6: Enable l2 cache ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

imx6: lowlevel_init: Fix workaround for new i.MX6s chips ...

This errata workaround was introduced for i.MX6Q, i.MX6D and i.MX6SL.
Old revisions of i.MX6s chips had no problems with the PFD resets.

In a newer i.MX6s revision I had issues with this code when booting in
internal boot mode from NAND or in serial downloader mode. FUSE mode
worked fine although it jumped directly to serial downloader mode.

This patch executes the PFD workaround only for i.MX6Q and i.MX6D which
fixes the issues I saw.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

sizes.h: move include/sizes.h to include/linux/sizes.h ...

This file originates in Linux.  Linux has it under include/linux/
directory since commit dccd2304cc90.
Let's move it to the same place as well in barebox.

This commit was generated by the following commands:

  find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:'
  git mv include/sizes.h include/linux/

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: Add i.MX6sx support ...

Add some cpu type defines and clock support. The clock support
is very different from other i.MX variants, so it's a separate
file, like done in the kernel.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: imx6: move imx6_init_lowlevel to single initcall ...

Instead of repeating the same lowlevel init for every board
move it to it's own initcall.

Avoids code bloat and shaves off almost 1.5kB of uncompressed
barebox size for a default imx_v7_defconfig build.

For boards wherethe hostname setup was done in  the postcore
initcall we move this to a device initcall to get it out of
the way.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

imx6: add new chip revisions ...

Add new chip revisions for the new tap-out TO1.5 (i.MX6Q/D) and TO1.2
(i.MX6DL/S)

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority ...

This is needed so that the IPU framebuffer scanout cannot be
starved by VPU or GPU activity.
Some boards like the SabreLite and SabreSD seem to set this in
the DCD already, but the documented register reset values do not
contain the necessary settings.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6: correct work flow of PFDs from uboot-sources ...

PFDs need to be gate/ungate after PLL lock to reset PFDs to right state.
Otherwise PFDs may lose correct state in state-machine, then no output
clock.
For i.MX6DL and i.MX6SL, ROM have taken care of PFD396 already since the
bus clock needs it.

This patch is backported from
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/cpu/arm_cortexa8/mx6/generic.c?h=imx_v2009.08_3.0.35_4.1.0&id=b7c5bad

And resolve issues with booting from MMC/SD cards

Signed-off-by: Jesús Guitarte <jguitarte@data-modul.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: Add correct SoC type detection for i.MX6 ...

Using the ANATOP_SI_REV register we can only distinguish between
i.MX6q/d and i.MX6dl/s SoCs. Take the number of cores into account
to get the exact SoC type.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6: Add cputype detection ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: centralize i.MX startup ...

Each i.MX SoC has its own SoC initcall. To ease multi SoC support
move it to a single initcall.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>