nand: mrvl: use ERR_CAST() for returning error pointers ...

ERR_CAST exists to return error pointers as error pointers without
casting them explicitly to the correct pointer type.

Also this Fixes:
In function 'alloc_nand_resource':
warning: return makes pointer from integer without a cast

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

driver: replace dev_request_mem_region with dev_request_mem_resource ...

dev_request_mem_region doesn't work properly one some SoCs on which
PTR_ERR() values clash with valid return values from dev_request_mem_region.
Replace them with dev_request_mem_resource where possible.

This patch has been generated with the following semantic patch:

// <smpl>
@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores)) {
...
-	return PTR_ERR(io);
-}
+	return PTR_ERR(iores);
+}
+io = IOMEM(iores->start);
...+>
}

@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores))
-	return PTR_ERR(io);
-}
+	return PTR_ERR(iores);
+io = IOMEM(iores->start);
...+>
}

@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
-	ret = PTR_ERR(io);
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores)) {
+	ret = PTR_ERR(iores);
...
}
+io = IOMEM(iores->start);
...+>
}

@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores))
+	return PTR_ERR(iores);
+io = IOMEM(iores->start);
...+>
}

@@
identifier func;
@@
func(...) {
<+...
struct resource *iores;
-struct resource *iores;
...+>
}
// </smpl>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U ...

This adds optimized timings for Samsung K9K8G08U 1Gb NAND flash.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP ...

Marvell PXA3xx and Armada 370/XP share the same NAND controller IP
with some minor differences. With support for controller IP v2, now
allow to build the driver on Armada 370/XP.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Add support for NDCB3 register ...

Newer versions of PXA3xx NAND controller support a 4th Command Buffer
register. Add the required HWFLAGS and additional write to NDCB0.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Add support for HW BCH ECC ...

Add support for HW BCH ECC for those HW versions that support it.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC ...

Add support for 8bit HW ECC modes supported by later IP versions.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECC ...

Add support for 4bit HW ECC modes supported by later IP versions.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions ...

Marvell PXA3xx NAND flash controller IP has been reused in later SoCs
with additional HW features. Add HW BCH ECC as the first known HW
difference.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths ...

Newer versions of Marvell PXA3xx NFC also support BCH and therefore
higher ECC strengths than 1. Prepare for different ECC strength by
factoring out ECC init into separate functions by strength. Also,
add a new host variable that indicates BCH ECC.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Get ecc parameters from DT ...

With DT helpers for ECC step size and strength, now use them on
Marvell NAND driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Fix num-cs property parsing ...

The "num-cs" property does not encode flashes CS line but number
of available CS signals. Fix wrong property parsing to ->cs by
adding proper ->num_cs variable to host struct.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Protect mrvl_nand_probe_dt ...

Parsing DT nodes if CONFIG_OFTREE isn't enabled is pointless, also
we should prefer potential platform_data passed earlier.
Protect mrvl_nand_probe_dt by bailing out early if either
CONFIG_OFTREE is not enabled or dev's platform_data is non-NULL.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase ...

Marvell NAND controller allows to enable an Auto Read Status feature
that will automatically monitor NAND status during Erase and Program
operations. Ready bit in status register will be set after the
controller is sure the NAND device has finished the operation and
saves us from guessing the real timeout values.

Using the Auto Read Status feature prevents timeout issues on the
two operations with none or wrong timing register setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00 ...

If OOB data is not required on page program, we have to clear
the corresponding data with 0xff instead of 0x00.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand_mrvl_nfc: Use common clock for core clock ...

With PXA3xx now providing a common clock for the NAND clock, use it
and get rid of the mach/clock.h. This will allow Marvell Armada 370/XP
to reuse the same driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand: mrvl-nand: create initial empty bbt ...

When creating an initial bad blocks table, create it empty. This is
necessary because when the bad block table blocks are not
initialized (all ff) while some partitions are, all the blocks which
have an OOB data not beginning with 0xff 0xff will be marked as bad
blocks in the initial bad blocks scan.

As a consequence, any existing blocks are impossible to erase
anymore. Fix this by fixing the BBT creation flag.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand: add mrvl-nand driver ...

The driver is taken from the Linux kernel, with the following changes :
 - all DMA removed
 - all asynchronous handling removed, including the interrupt handler,
   and the asynchronous state handling
 - pxa armada support removed

Most the kernel structure was kept, to ease up future fixes integration
from the kernel driver.

The driver is tested on a pxa3xx system development
board (aka. zylonite), and reading, writing, erasing, and bad block
management were tested.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>