This adds base support for the i.MX8MP SoC. Not much to do here as this
SoC is quite similar to the i.MX8M. This adds:

- Kconfig symbols
- bootsource detection
- register base address defines
- iomux defines

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>

This adds support for the i.MX8MM.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

barebox_arm_reset_vector() is a global function but we never provided a
prototype anywhere. The prototypes differ for the different boards, so
to provide a common prototype we must harmonize them.

void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)

Should be suitable for all boards.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Since __imx_cpu_type won't be initialized until
imx_init()@postcore_initcall is executed cpu_is_mx8mq() will only work
correctly at core_initcall level so long as imx_cpu_type does not
resolve into __imx_cpu_type. This is currently the case and
imx8mq_init_syscnt_frequency() works as expected, but it probably
won't be in the future.

To avoid this problem introduce imx8mq_cpu_lowlevel_init() and do
system counter frequency initialization there. Also convert all of the
i.MX8MQ boards to use this new function.

Fixes: 5691aed9a ("ARM: i.MX8MQ: Check CPU type in imx8mq_init_syscnt_frequency()")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

We need to make sure that CNTFRQ is initialized before corresponding
clocksource driver tries to use it, otherwise we'll end up crashing
due to division by zero.

We can't convert imx7_timer_init() to be an initcall since it is an
i.MX7 specific task, but CPU type information won't be availible until
after imx_init() gets executed at postcore_initcall() level. To solve
this move all of the necessary code to be a part of
imx7_cpu_lowlevel_init().

Note, that original code both hardcoded frequency value to 8MHz as
well as tried to write it to the first element of the frequency mode
table which appears to be read-only on i.MX7. So while we are at it,
simplify the code by adding set_cntfrq() implementation for ARMv7 and
copy the code we already using for i.MX8MQ.

Fixes: dece70752 ("clocksource: Enable architected timer support for CPU_V7")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mach/generic.h provides prototypes for functions that mach-imx/cpu_init.c
implements, so include the header file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Since 4.18-rc1 kernel the following warning is seen on i.MX51 and
i.MX53:

CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable

Implement the suggested workaround by setting the IBE bit in the
auxiliary control register, which allows the kernel to flush the
BTB properly.

Based on commit 7b37a9c732bf ("ARM: Introduce ability to enable ACR::IBE
on Cortex-A8 for CVE-2017-5715") from U-Boot.

With this patch applied the kernel now reports:

CPU0: Spectre v2: using BPIALL workaround

Tested on a imx51 babbage.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

On i.MX6ul(l) (Cortex A7) We have to set the SMP bit before
enabling the caches, otherwise they won't work. Add a SoC specific
lowlevel_init function to be called by the i.MX6ul(l) boards.

Since this is a quirk of the Cortex A7 core we put the functionality
into a separate function to be reused by other Cortex A7 cores.

Change existing i.MX6ul(l) boards to use the new initialisation
function. It seems this is only needed when booting from USB,
in other boot modes the ROM will already have done the initialisation.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add very basic functions to support VF610 family.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This is similar to what we do on imx6 and makes sure we
apply the errata workarounds early.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Enables all relevant errata workarounds for the
i.MX6 SoC.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>