PCI: dwc: tune down link up messages ...

This function may be called repeatedly while establishing the link,
so printing a message each time a working link is found can add quite
a bit of noise. Tune those messages down to the debug level.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Replace lower into upper case characters ...

Port of a Linux commit b4a8a51

  Replace of all initial lowercase character in comments and debug messages
  to uppercase to maintain coherence.

  Fix messages coherence within the DesignWare driver.

  Fix code style on dw_pcie_irq_domain_free() function.

  Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate ...

Port of a Linux commit 8cfab3c

  Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license.

  Remove the boilerplate GPL version 2 language, relying on the assertion in
  b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
  files with no license") that the SPDX identifier may be used instead of the
  full boilerplate text.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Fix typos and whitespace errors ...

Port of a Linux commit 96291d5

  Fix various typos and whitespace errors:

    s/Synopsis/Synopsys/
    s/Designware/DesignWare/
    s/Keystine/Keystone/
    s/gpio/GPIO/
    s/pcie/PCIe/
    s/phy/PHY/
    s/confgiruation/configuration/

  No functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static ...

Port of a Linux commit 684a3a9

  Helper functions dw_pcie_prog_*_atu_unroll() don't need to be in global
  scope, so make them static.

  Cleans up sparse warnings:
    - symbol 'dw_pcie_prog_outbound_atu_unroll' was not declared. Should it be static?
    - symbol 'dw_pcie_prog_inbound_atu_unroll' was not declared. Should it be static?

  Signed-off-by: Carlos Palminha <palminha@synopsys.com>
  [bhelgaas: rewrap to fit in 80 columns]
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically ...

Port of a Linux commit e9be4d7

  The ATU CTRL2 register is 32 bits, and bits other than the enable bit may
  be set.  To check whether the ATU is enabled or not, we should test the
  enable bit specifically.

  Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Move _unroll configurations to a separate function ...

Port of a Linux commit edd45e3

  No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to
  dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these
  functions are used to perform only outbound configurations. Also move
  these _unroll configurations to a separate function.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes ...

Port of a Linux commit a509d7d

  Previously dbi accessors can be used to access data of size 4 bytes. But
  there might be situations (like accessing MSI_MESSAGE_CONTROL in order to
  set/get the number of required MSI interrupts in EP mode) where dbi
  accessors must be used to access data of size 2. This is in preparation
  for adding endpoint mode support to designware driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Niklas Cassel <niklas.cassel@axis.com>
  Cc: Jingoo Han <jingoohan1@gmail.com>
  Cc: Joao Pinto <Joao.Pinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Modify dbi accessors to take dbi_base as argument ...

Port of a Linux commit b50b2db

  dwc has 2 dbi address space labeled dbics and dbics2. The existing helper
  to access dbi address space can access only dbics. However dbics2 has to
  be accessed for programming the BAR registers in the case of EP mode. This
  is in preparation for adding EP mode support to dwc driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Niklas Cassel <niklas.cassel@axis.com>
  Cc: Jingoo Han <jingoohan1@gmail.com>
  Cc: Joao Pinto <Joao.Pinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Split pcie-designware.c into host and core files ...

Port of a Linux commit feb85d9

  Split pcie-designware.c into pcie-designware-host.c that contains the host
  specific parts of the driver and pcie-designware.c that contains the parts
  used by both host driver and endpoint driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Fix style errors in pcie-designware.c ...

Port of a Linux commit 314fc85

  No functional change. Fix all checkpatch warnings and check errors in
  pcie-designware.c

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-By: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() ...

Port of a Linux commit 5f334db

  The "num-lanes" DT property is parsed in dw_pcie_host_init(). However
  num-lanes is applicable to both root complex mode and endpoint mode. As a
  first step, move the parsing of this property outside dw_pcie_host_init().
  This is in preparation for splitting pcie-designware.c to pcie-designware.c
  and pcie-designware-host.c

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Split struct pcie_port into host-only and core structures ...

Port of a Linux commit 442ec4c

  Keep only the host-specific members in struct pcie_port and move the common
  members (i.e common to both host and endpoint) to struct dw_pcie.  This is
  in preparation for adding endpoint mode support to designware driver.

  While at that also fix checkpatch warnings.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  CC: Jingoo Han <jingoohan1@gmail.com>
  CC: Richard Zhu <hongxing.zhu@nxp.com>
  CC: Lucas Stach <l.stach@pengutronix.de>
  CC: Murali Karicheri <m-karicheri2@ti.com>
  CC: Minghuan Lian <minghuan.Lian@freescale.com>
  CC: Mingkai Hu <mingkai.hu@freescale.com>
  CC: Roy Zang <tie-fei.zang@freescale.com>
  CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  CC: Niklas Cassel <niklas.cassel@axis.com>
  CC: Jesper Nilsson <jesper.nilsson@axis.com>
  CC: Joao Pinto <Joao.Pinto@synopsys.com>
  CC: Zhou Wang <wangzhou1@hisilicon.com>
  CC: Gabriele Paoloni <gabriele.paoloni@huawei.com>
  CC: Stanimir Varbanov <svarbanov@mm-sol.com>
  CC: Pratyush Anand <pratyush.anand@gmail.com>

For convenience sake, commit c046406

  PCI: dwc: Fix crashes seen due to missing assignments

  Fix the following crash, seen in dwc/pci-imx6.

    Unable to handle kernel NULL pointer dereference at virtual address 00000070
    pgd = c0004000
    [00000070] *pgd=00000000
    Internal error: Oops: 805 [#1] SMP ARM
    Modules linked in:
    CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.10.0-09686-g9e31489 #1
    Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
    task: cb850000 task.stack: cb84e000
    PC is at imx6_pcie_probe+0x2f4/0x414
    ...

  While at it, fix the same problem in various drivers instead of waiting for
  individual crash reports.

  The change in the imx6 driver was tested with qemu. The changes in other
  drivers are based on code inspection and have been compile tested only.

  Fixes: 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures")
  Signed-off-by: Guenter Roeck <linux@roeck-us.net>
  Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>  # designware-plat
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

was squashed into this one as well.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() ...

Port of a Linux commit 40f67fb

  No functional change. Get device pointer at the beginning of
  dw_pcie_host_init() instead of getting it all over dw_pcie_host_init().
  This is in preparation for splitting struct pcie_port into host and core
  structures (once split pcie_port will not have device pointer).

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Rename cfg_read/cfg_write to read/write ...

No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do
  anything specific to access configuration space. It can be just renamed to
  dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-By: Joao Pinto <jpinto@synopsys.com>
  CC: Jingoo Han <jingoohan1@gmail.com>
  CC: Murali Karicheri <m-karicheri2@ti.com>
  CC: Stanimir Varbanov <svarbanov@mm-sol.com>
  CC: Pratyush Anand <pratyush.anand@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Move register defines to designware header file ...

Port of a Linux commmit b90dc39

  No functional change. Move the register defines and other macros from
  pcie-designware.c to pcie-designware.h. This is in preparation to split the
  pcie-designware.c file into designware core file and host-specific file.

  While at that also fix a checkpatch warning.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-By: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Check for iATU unroll only on platforms that use ATU ...

Port of a Linux commit a782b5f

  Previously we checked for iATU unroll support by reading PCIE_ATU_VIEWPORT
  even on platforms, e.g., Keystone, that do not have ATU ports.  This can
  cause bad behavior such as asynchronous external aborts:

    OF: PCI:   MEM 0x60000000..0x6fffffff -> 0x60000000
    Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
    pgd = c0003000
    [00000000] *pgd=80000800004003, *pmd=00000000
    Internal error: : 1211 [#1] PREEMPT SMP ARM
    Modules linked in:
    CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-00009-g6ff59d2-dirty #7
    Hardware name: Keystone
    task: eb878000 task.stack: eb866000
    PC is at dw_pcie_setup_rc+0x24/0x380
    LR is at ks_pcie_host_init+0x10/0x170

  Move the dw_pcie_iatu_unroll_enabled() check so we only call it on
  platforms that do not use the ATU.  These platforms supply their own
  ->rd_other_conf() and ->wr_other_conf() methods.

  [bhelgaas: changelog]
  Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature")
  Fixes: 416379f9ebde ("PCI: designware: Check for iATU unroll support after initializing host")
  Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-By: Joao Pinto <jpinto@synopsys.com>
  CC: stable@vger.kernel.org      # v4.9+

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments ...

Port of a Linux commit f5acb5c

  Swap order of dw_pcie_readl_unroll() arguments to match the "dev, pos, val"
  order used by pci_write_config_word() and other drivers.  No functional
  change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Uninline register accessors ...

Port of a Linux commit 3d46993

  The register accessors are not performance critical and small enough that
  the compiler can inline them itself if it makes sense.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc() ...

Export dw_pcie_readl_rc() and dw_pcie_writel_rc().  Many other drivers can
  use these instead of implementing their own versions.  No functional change
  intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments ...

Port of a Linux commit ad88021

  Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val"
  order used by pci_write_config_word() and other drivers.  No functional
  change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces ...

Port of a Linux commit 7e00dfd

  The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers
  allow a driver to override the default DesignWare register accessors.

  Make the signature of the override functions the same as the default
  accessors.  This makes the default dw_pcie_readl_rc() and the corresponding
  override more structurally similar: both will compute the final register
  address with "pp->dbi_base + reg".  Previously dw_pcie_readl_rc() computed
  the address and passed it to the override.

  No functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll() ...

Port of Linux commit a26e010

  dw_pcie_readl_unroll() and dw_pcie_writel_unroll() duplicate what
  dw_pcie_readl_rc() and dw_pcie_writel_rc() already do, so call them
  directly.

  [bhelgaas: reworked into patch series]
  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device() ...

Port of a Linux commit 1034023

  Rename dw_pcie_valid_config() to dw_pcie_valid_device() and use the result
  directly as a boolean value instead of testing against 0.  No functional
  change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs' ...

Port of a Linux commit 68a0bfe

  When we have only two view ports in a DesignWare PCIe platform, iatu0
  is used for both CFG and IO accesses.  When CFGs are sent to peripherals
  (e.g., lspci), iatu0 frequently switches between CFG and IO.

  For such scenarios, a MEMORY might be sent as an IOs by mistake.
  Considering the following configurations:

    MEMORY  ->   BASE_ADDR: 0xb4100000, LIMIT: 0xb4100FFF, TYPE=mem
    CFG     ->   BASE_ADDR: 0xb4000000, LIMIT: 0xb4000FFF, TYPE=cfg
    IO      ->   BASE_ADDR: 0xFFFFFFFF, LIMIT: 0xFFFFFFFE, TYPE=io

  Suppose PCIe has just completed a CFG access.  To switch back to IO, it
  sets the BASE_ADDR to 0xFFFFFFFF, LIMIT 0xFFFFFFFE and TYPE to IO.  When
  another CFG comes, the BASE_ADDR is set to 0xb4000000 to switch to CFG.  At
  this moment, a MEMORY access shows up, since it matches with iatu0 (due to
  0xb4000000 <= MEMORY BASE_ADDR <= MEMORY LIMIT <= 0xFFFFFFF), it is treated
  as an IO access by mistake, then sent to perpheral.

  This patch fixes the problem by exchanging the assignments of `MEMORYs' and
  `CFGs/IOs', which assigning MEMORYs to iatu0, CFGs and IOs to iatu1.

  We can still have issues with IO transfer, however memory transfer is used
  predominantly therefore we are just minimizing the risk of failure.
  Actually, we can not do much when we have only two viewports.  We can
  either not allow the less frequent IO transfers at all, or can live with a
  remote possibility of getting it corrupted.

  Signed-off-by: Dong Bo <dongbo4@huawei.com>
  [pratyush.anand@gmail.com: Modified commit log to capture remote risk]
  Signed-off-by: Pratyush Anand <pratyush.anand@gmail.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2 ...

Port of a Linux commit fe48cb8

  Most of the platforms have 3 or more viewports.  For such platforms, We do
  not need to share viewports between IO and CFG.  Assign viewport 2 to IO
  transactions in such cases.

  Tested-by: Dong Bo <dongbo4@huawei.com>
  Signed-off-by: Pratyush Anand <pratyush.anand@gmail.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Rob Herring <robh@kernel.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Check LTSSM training bit before deciding link is up ...

Port of a Linux commit 01c0767

  The link may be up but still in link training.  In this case, we can't
  think the link is up and operating correctly.  Teach dw_pcie_link_up() to
  be aware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.

  Also rewrite PCIE_PHY_DEBUG_R1_LINK_UP definition so that it's consistent
  with other macros.

  Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Add iATU Unroll feature ...

Port of a Linux commit a0601a4

  Add support for the new iATU Unroll mechanism that will be used from Core
  version 4.80.  The new Cores can support either iATU Unroll or the "old"
  iATU method, now called Legacy Mode.  The driver is perfectly capable of
  performing well for both.

  [bhelgaas: split ATU enable timeout to separate patch]
  Signed-off-by: Joao Pinto <jpinto@synopsys.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

To avoid breaking i.MX6 PCIE support commit
416379f was squashed here as well

  PCI: designware: Check for iATU unroll support after initializing host

  dw_pcie_iatu_unroll_enabled() reads a dbi_base register.  Reading any
  dbi_base register before pp->ops->host_init has been called causes
  "imprecise external abort" on platforms like ARTPEC-6, where the PCIe
  module is disabled at boot and first enabled in pp->ops->host_init.  Move
  dw_pcie_iatu_unroll_enabled() to dw_pcie_setup_rc(), since it is after
  pp->ops->host_init, but before pp->iatu_unroll_enabled is actually used.

  Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature")
  Tested-by: James Le Cuirot <chewi@gentoo.org>
  Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Wait for iATU enable ...

Port of a Linux commit d8bbeb3

  Add a loop with timeout to make sure the iATU is really enabled before
  subsequent config and I/O accesses.

  [bhelgaas: split to separate patch, use dev_err() instead of dev_dbg()]
  Signed-off-by: Joao Pinto <jpinto@synopsys.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: designware: Move link wait definitions to .c file ...

Port of a Linux commit c388de1

  Move the link wait sleep definitions to the .c file as suggested by
  Jisheng Zhang in a previous patch.

  Signed-off-by: Joao Pinto <jpinto@synopsys.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  CC: Jisheng Zhang <jszhang@marvell.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>