After the PCIe switch has been scanned its GPIOs need to be
configured as output-high to release the devices behind the
switch from their reset state and make them discoverable to
the bus scan.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Older boards before revision E don't have the external watchdog signal
wired up to the PMIC, so they must use watchdog 1, which is able to
reset the SoC internally.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

For now only the Quad 1GB variant is supported.

Tested:
- starting barebox over USB
- writing barebox to NAND with barebox_update
- starting Linux kernel over TFTP

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>