pci: add quirk infrastructure ...

This is a cut down version of the Linux kernel PCI quirk infrastructure,
which allows to register and execute some fixups before the driver is
loaded.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: link PCI devices with potentially existing OF nodes ...

The document "PCI Bus Binding to: IEEE Std 1275-1994 Standard for Boot
(Initialization Configuration) Firmware" describes how the PCI topology
can be described in the DT, in order to augment the PCI devices with
additional information via DT properties.

This patch links OF nodes to the corresponding PCI devices if they
exist, allowing PCI device drivers to query DT information like any
platform device.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: split PCI hierarchy enumeration and config from device registration ...

This gets rid of some of the special cases in the bus scanning function
by splitting hierarchy enumeration and configuration and the actual
device registration into 2 passes.

This ensures that the PCI hierarchy below a root port is completely
set up before any device driver is probed.

This simplifies the code and makes it less error prone, while moving
the PCI address space layout closer to the one used by Linux.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: align BAR address to BAR size ...

PCI BARs require their address to be at least aligned to their
size, otherwise address decoding will fail as the base address
gets rounded down.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: align address range before scanning bridge ...

Otherwise we may end up with a too low base address and push
requests for the upstream bus onto the downstream side.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: only check specific flag for 64bit BAR ...

The memory type may include other flags, so just check for
the 64bit allocation flag to see if the BAR is a 64bit one.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: add some useful debug output ...

This makes diagnosing problems in address space allocation
much easier.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: remove bogus host bridge setup skipping ...

Apparently this was here to fix issues with some QEMU version,
but hasn't worked in the intended way for a long time. The probe
code should be mature enough by now, so this workaround isn't
needed anymore.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: rework BAR size calculation ...

The probe code now does a much better job at detecting bad BARs.
Also make sure to preserve any previous content of the BAR
registers if we don't relocate them.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: fill in bus primary field ...

This was erroneously left uninitialzed as nothing was using it.
The i.MX6 PCI driver needs this to be filled properly to decide
if a config space access is allowed for a specific devfn.

This fixes PCI enumeration on the Gateworks GW54xx board.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: register and active bridge device before proceeding to scan ...

The bridge device needs to be registered and activated before
the scanning can proceed, as the bridge is the parent for other
devices.

This fixes a NULL ptr derefernce when scanning PCI hierarchies
with bridges behind bridges.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/pci'

pci: make sure to activate devices on the root bus ...

Commit b8a1bb1dd215 (pci: defer device registration until after bridge setup)
changed the activation order of devices, so that bridges above the devices could
be configured properly before activating the devices below. This commit failed
to acknowledge that there may be devices located directly on the root bus without
any bridge in between and so those devices would never get enabled.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

pci: fix copy-paste bug ...

Test for the correct resource before derefencing it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: Use standard pr_debug ...

Use pr_debug instead of custom DBG macro.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: fix bad bugs in bridge setup code ...

Add the required brackets, so that we don't write unused registers
with potentially bogus values.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

sizes.h: move include/sizes.h to include/linux/sizes.h ...

This file originates in Linux.  Linux has it under include/linux/
directory since commit dccd2304cc90.
Let's move it to the same place as well in barebox.

This commit was generated by the following commands:

  find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:'
  git mv include/sizes.h include/linux/

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: align bridge windows ...

The bridge filtering logic needs a minimum
alignment of 1MB for mem and 4KB for io resources.
Take this into account while assigning resources
to devices in oredr to not produce overlapping
windows between different bridges.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: correct BAR size calculation ...

The previous math would return negative sizes
for some BARs.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: track parent<->child relationship ...

So that PCI devices hang down from bridges and root
bridges down from the PCI host controller when
calling devinfo.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: defer device registration until after bridge setup ...

Otherwise the drivers for a device may probe before the
devices parent bridge is fully configured, which leads
to errors when accessing the BARs.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: setup bridges and traverse buses behind them ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: properly populate prefetchable BARs ...

Some host controllers provide a prefetchable
memory area and devices will prefer this for
some of their BARs.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: add resource enum ...

Makes things way clearer than juggling numbers.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: split out device init ...

To make it reusable and the code more readable.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: set auto-incremented bus number ...

When using more than one PCI bus, we have to assign unique numbers
to each bus. Use an auto-incremented bus index and assign it to
each registered bus. Also, allow the PCI host controller to update
internal registers by calling set_busno with assigned bus number.

While at it, add pci_controller struct to set_busno callback,
add a back reference to pci_controller to pci_bus, and clean up
unused left-overs from Linux import.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: ensure device does ignore BAR mangling ...

Disable access to PCI devices I/O and memory regions while
mangling BAR registers.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: register device after BAR setup ...

As soon as pci_register_device is called, a potential driver
will access its registers. This requires BARs to be set up
properly, so move pci_register_device after BAR setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: pci_scan_bus: respect 64b BARs ...

In PCI 64-bit BARs span two 32-bit BARs, therefore if BAR type
indicates a 64-bit BAR we have to skip the next BAR register.
While at it, also set proper IORESOURCE flags for I/O and
32b MEM.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: pci_alloc_bus(): use xzalloc() instead of kzalloc() ...

Also drop redundant xzalloc() result check
as xzalloc() does not return in case of memory allocation error.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>