The relocator is not able to patch properly new location of
the stack. To make it work properly it is better to disable
HAVE_CONFIGURABLE_MEMORY_LAYOUT.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This patch came out of discussions in the 'MIPS parallel build breakage' e-mail thread:

    http://lists.infradead.org/pipermail/barebox/2018-March/032251.html

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS `lw` instruction loads a 32 bit word from memory on both 32 bit and 64 bit
systems. On the other hand LONGSIZE is either 4 or 8 depending on selected code
model. This discrepancy causes copy_to_link_location failure on 64 bit systems.

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Barebox' PBL is able to initialize SoC's memory controller,
but it can be used only if PBL runs from ROM or on-chip SRAM.
MIPS architecture standard boot vector is 0xbfc00000
so on most MIPS SoCs all addresses higher than 0xbfc00000
belong to boot ROM or on-chip SRAM. Thus there's a
simple criterion to check if PBL runs from ROM: just
check if current PC is higher than 0xbfc00000.
Some MIPS boards have ROM start address lower than 0xbfc00000
so it's reasonable to make ROM start address checking board-dependant.

The pbl_blt macro checks if current pc is lower than
the first argument (ROM start address). If so then
next instruction executed is defined by the second argument
of the macro.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Tested-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This commit clears ERL (ERror Level) flag on start.
If this flag is set then we get 'TLB miss on load or ifetch'
just after return from exception.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The mips_barebox_10h macro inserts at offset 0x10
of the barebox image the string 'barebox ' followed
by compile time version mark.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The generated label usage make possible
to use the ADR macro many times.

If we don't use a generated label and we try
to use the ADR macro second time then we get

   Error: symbol `_pc' is already defined

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

We already have the LONGSIZE macro definition in <asm/asm.h>.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This patch is based on ARM pbl support and allows
creating a pre-bootloader binary for compressed image.

For different MIPS SoCs (or even for different boards based
 on the same SoC) the operations carried on in start-pbl.S
can be very different. The additional constraints can be imposed
on the size of the boot code or the special magic labels in
the beginning of the boot code; In some cases it could be
necessary to show CPU is alive as early as possible
(transmit a char via UART or blink a LED).
So the demands for pbl start operation can be very different.

E.g. malta board store boot code at the NOR flash mapped
to the MIPS power-on address (0xbfc00000); it is the most
simple case: we need just copy pbl image from direct-mapped
flash to RAM and jump there.

The XBurst-powered boards store boot code in the beginning
of a NAND flash or in the beginning of SD/MMC card.
In this case we must use simple and short NAND or SD/MMC access
routines to copy pbl image to RAM.

To meet so different demands a simple technique is selected:

* MIPS pbl entry point located in file arch/mips/boot/start-pbl.S.

* MIPS pbl code (see start-pbl.S) assumes that every pbl-enabled
board has a arch/mips/boards/<BOARD>/include/board/board_pbl_start.h
header file. This file must contain definition of
the board_pbl_start macro. This macro is used as start of pbl image;

* the most popular asm routines (stack setup, relocation to link
address, NS16550 initialization (WIP) and so on) are containt
in the arch/mips/include/asm/pbl_macros.h header file.
So board pbl macro can use it if necessary.
It is possible to create similar headers with macros for each
specific SoC; so even if we have many different boards based
on the same SoC the board_pbl_start macro for every board
can be short and clear.

* after board-specific initialization the stack pointer
is initialized and pbl C code is started.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>