To prepare PCIe device id fixups, move PCIe register defines
to a common location.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The initialisation of the memory nodes on mvebu is a bit
compilcated:

pure_initcall(mvebu_memory_fixup_register)
	of_register_fixup(mvebu_memory_of_fixup, NULL)
core_initcall(kirkwood_init_soc)
	mvebu_set_memory()
core_initcall(of_arm_init)
	of_fix_tree()
		mvebu_memory_of_fixup()

First a mvebu common of_fixup function is registered, then the SoC
calls mvebu_set_memory which stores the memory base and size in global
variables. Afterwards the of_fixup is executed which fixes the memory
nodes according to the global variables.

Instead register a SoC specific fixup which directly calls mvebu_set_memory
with the memory base and size as arguments:

pure_initcall(kirkwood_register_soc_fixup);
	of_register_fixup(kirkwood_init_soc, NULL);
core_initcall(of_arm_init)
	of_fix_tree()
		kirkwood_init_soc()
			mvebu_set_memory(phys_base, phys_size);

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mvebu has a reset_cpu function per SoC this does not work when multiple
SoCs are selected, so add a common reset_cpu function which calls into
the SoC specific ones.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

On Marvell MVEBU SoCs memory size is set up by BootROM and can be read
from SoC's RAM controller. With early DT fixups available, set corresponding
DT node to reflect accessible amount of directly attached RAM.

This patch also removes non-DT call to arm_add_mem_device to silence a
warning about request_region conflict due to adding a mem device twice.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Marvell MVEBU SoC id and revision can be read out from any PCIe port
registers. This adds corresponding code to read out id and revision
and provides a helper function for drivers to use it.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mach-mvebu has two files containing lowlevel code. Consolidate both into
mach-mvebu/lowlevel.c. Also put the now empty mach-mvebu/common.c into
non-lowlevel obj-y as it will be used for common non-lowlevel code later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Mostly to make it clear that boarddata needs to be
something we can dereference.

As this is a pretty invasive change, use the opportunity
to make the signature 64bit safe.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

At early stage after boot, all MVEBU SoCs are similar enough to have
a common lowlevel and barebox entry. We  also remap the internal register
base address to 0xf100000 as it gives some 512M more of contiguous address
space. As we cannot determine real memory size that early, we start with
a default memory size of 64M and probe correct size later in SoC init.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>