S3C24xx/NFC: Add OOB/ECC handling documentation for different NANDs ...

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

S3C24xx/NFC: Setup ECC handling in accordance to the kernel ...

Do the same ECC handling and ECC size in barebox than the kernel does.
Currently its done for S3C2440 based systems only, as I have no idea how to
manage it on a S3C2410 based system.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

S3C24xx/NFC: Consider correct NAND page size for boot. ...

When booting from NAND, its important to know the correct page size. When
the NAND is used as the boot source, four dedicated pins are used to configure
the correct page size and address cycles. These pins can be read back in one
of the NFC registers to parametrize the load function.

This patch also extends the read routine to support more than four address
cycles on demand.

BTW: At least some mini2440s are misconfigured to use five address cycles for
a NAND device that is known to need only four address cycles. In this case the
vendor is at our side: This NAND simply ignores any additional address cycles
than required.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

S3C24xx/NFC: Remove double function setup ...

Three lines above this setting is already done.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

S3C24xx/NFC: Remove dead code ...

Something was to be done here. But I do not remember what. As it works also
without it, remove this dead code.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

S3C24xx/NFC: Re-enable the controller after NAND boot test ...

After running the 'nand_boot_test' command, any usage of the NAND fails with
a IO error. This happens due to the load routine disables the NAND controller
after loading the image.

This patch re-enables the NAND controller again after running the test.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MACH-S3C2440: Speed up NAND controller for this CPU ...

The S3C2440 provides 32 bit access to the NAND's data. Add specific read
routines to speed up data reading and writing.

These routines are stolen from the Linux kernel.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MACH-S3C2440: Fix NAND controller for this CPU ...

There are a few but important differences in S3C2410 and S3C2440. This patch
fixes them for the S3C2440 CPU.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MACH-S3C24XX: Add support for flash based BBT ...

The default configuration of the current 2.6.37 kernel uses a flash based BBT.
So, barebox must also use one, to be in sync with the kernel about bad blocks
in the flash.

Due to the used OOB layout, the generic BBT description coming with the
framework can be used.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

nand_s3c2410: Fix sparse warnings. ...

Patch fix following sparse warnings:
drivers/mtd/nand/nand_s3c2410.c:125:9:
warning: incorrect type in argument 1 (different base types)
	expected void const volatile [noderef] <asn:2>*<noident>
	got unsigned long

Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

move drivers/nand to drivers/mtd/nand ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>