Converts the files that licensecheck can determine the license for. Also
convert to obvious right Copyright statements. Additionally some minor
code reformatting is done.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Since 4.18-rc1 kernel the following warning is seen on i.MX51 and
i.MX53:

CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable

Implement the suggested workaround by setting the IBE bit in the
auxiliary control register, which allows the kernel to flush the
BTB properly.

Based on commit 7b37a9c732bf ("ARM: Introduce ability to enable ACR::IBE
on Cortex-A8 for CVE-2017-5715") from U-Boot.

With this patch applied the kernel now reports:

CPU0: Spectre v2: using BPIALL workaround

Tested on a imx51 babbage.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM Cortex A8 errata 709718:
"Load and store operations to shared device memory
regions may not complete in program order"

We implement the recommended workaround in the bootloader
as it must be applied before enabling the MMU for the
first time.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Header only implementation, so they can be pulled
into the individual SoC cpu init functions.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>