At least some ath79 SoC have build in 32K RAM. It allow us to use
lowlevel portion of barebox to bootstrap the system by using JTAG
debugger (For example OpenOCD).
Since ath79 has no reliable way to stop the CPU execution before
reading SPI Flash, this can cause different issues. To avoid it, we
need to flash a execution trap with software debug breakpoint to the
flash.

The workflow should be as follow:
- After power on or reset the CPU will start execution of SPI flash.
  As soon as software debug breakpoint is executed, CPU will halt and
  notify OpenOCD about breakpoint event.
- OpenOCD will load reduced barebox to SRAM and execute it.
  This part will do all needed low level initialization - PLL, RAM and
  trigger second breakpoint event.
- OpenOCD will load full barebox version to the main RAM and start
  execution.

It can be used for bring-up, so no regular flashing is needed.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

this partition contains calibration data for WiFi and
some board specific data, like MAC address.

For now we care only about MAC.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Most of ar93xx SoCs seem to work only with spi.
spifash handler should be enough for now.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Use the mach-ath79 name for compatibility with linux kernel.

Signed-off-by: Du Huanpeng <u74147@gmail.com>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>