The actual RAM timings in the phyFLEX BSP are generated for 528 MHz RAM clock
frequency, but the i.MX 6Solo/DualLite has only a 400 MHz RAM clock. These new
timings are accompanied by a speed increase of approx 10%.

Signed-off-by: michael grassmann <michael.grassmann@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>

This makes the imxcfg files more readable and also makes it possible to
share more assignments between machines that just differ by the used
SoC. (Though I have to admit that in the cases converted here it just
more easily allows to see that the RAM config differs more than probably
necessary.)

This change is intended to have no effect on the built artifacts.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

The loadaddr in the flash-headers for the phyFLEX/phyCARD-i.MX6 was set
to 0x20000000 (512MiB). The start of the DDR memory in CPU's memory map
is 0x10000000 (256MiB). So the ROM loader loads the barebox image at the
memory position 256MiB and higher in the DDR memory.

This is a problem when the module doesn't have more than 256MiB of
memory. Therefore the loadaddr is set to the start of the DDR memory.

The patch was tested on a phyFLEX-i.MX6 Quad with 1GiB RAM on one bank
and on a phyCARD-i.MX6 Quad 1GiB RAM on two banks.

Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The main idea behind this patch is to avoid redundant code.  Because of
the module similarities of all i.MX6 based phytec boards, we can merge
its code.

The phytec-som-imx6 merges the code of all i.MX6 based phytec SOMs.  So
we will have only one "board" in the barebox for phyCARD-i.MX6 and
phyFLEX-i.MX6.

Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>