The CREDITS file was removed from barebox in 2015 by commit 6570288f2d97
("Remove the CREDITS file"). Remove references to it from several files.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Not all architectures are referencing the image_end section from
code, in which case the linker is free to drop the section, which
then messes up the calculation of the _barebox_image_size linker
variable.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Create a sha256sum of the compressed barebox image and always add it to
the PBL. We also add a custom linker section for ARM, to retrieve the
sha256sum for piggydata verification.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signing on i.MX8MQ is done by signing only the PBL, since the DRAM is
not available on early start and the SRAM is not big enough to contain
the whole image. Reserve a CSF area between PBL and the piggydata, to
ensure that the CSF area can be loaded into SRAM.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PBL images are often constrained in size by limitations exposed by
the SoCs SRAM size or partition sizes on the boot device. So far
we tried to configure these limits in Kconfig, but with PBL multi
images and thus different limitations for the different supported
images this no longer works. This patch has another approach for
it:

During build time make variables containing the relevant sizes for
each image are created. These are:

PBL_CODE_SIZE_$(symbol)
PBL_MEMORY_SIZE_$(symbol)
PBL_IMAGE_SIZE_$(symbol)

PBL_CODE_SIZE_$(symbol) contains the pure code size of the PBL, it
should be smaller than the available SRAM during boot. Normally the
PBL's bss segment also needs to be in the initial SRAM, for this
case PBL_MEMORY_SIZE_$(symbol) is the relevant variable.
PBL_IMAGE_SIZE_$(symbol) contains the full size of the PBL image
including the compressed payload (but without any image headers
created later by SoC specific image tools).

$(symbol) is a placeholder for the start symbol used for this PBL image,
thus for the i.MX53 QSB with entry start_imx53_loco

PBL_CODE_SIZE_start_imx53_loco

will be created. The images/Makefile.* can use these variables directly
to check sizes or specify the same variables with a "MAX_" prefix. So
when images/Makefile.imx specifies

MAX_PBL_CODE_SIZE_start_imx53_loco = 0x10000

then the build system will make sure that the PBL code for the QSB will
not get bigger than 64KiB.

Also included in this patch are the size restrictions for the i.MX8MQ
images as an example how to use this.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This reverts commit 5c0e165.

The fix_size scripts is not necessary for newer ARM toolchains,
it is however necessary for the older ARM toolchains (gcc-5 and older).

The original reason to drop fix_size was that it doesn't work on MIPS.
With this patch we add the -i flag so that we ignore unknown images
and can succesfully build MIPS images.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Now that we compile the compressed binary into the decompressor we
no longer need fix_size but can use the linker to fill in the image
size into the binary.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The way we assemble the multi images on ARM is rather complicated and
error prone. We currently cat the compressed barebox image behind the
PBL executable and need some magic to obtain the size of the payload and
also have to do tricks to reliably get a pointer to the compressed
image.

This patch switches over to compile the compressed payload into the PBL
image itself which has proven to work for the single PBL case and for
the ARM Linux Kernel aswell.

The goal is to unify the single PBL and the multi PBL cases together in
the future to get an easier startup path for ARM.

This patch has been tested on the i.MX53 QSB, i.MX53 Vincell, Beaglebone
black (both MLO and 2nd stage) and a Phytec phyFLEX i.MX6 board.

SoCFPGA Arria10 has also be changed slightly with this patch. We used to
generate a single image (barebox-socfpga-achilles.img) which was
used as xload image and full image. We now instead generate two images:
barebox-socfpga-achilles-xload.img and barebox-socfpga-achilles.img, the
former loaded by the ROM and the latter loaded by the xload image.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The current way to calculate the compressed image position works
with the OSELAS toolchains, but not with the Debian/Ubuntu toolchains.
For these toolchains &image_end_marker already returns the correct
address, adding global_variable_offset() to it is wrong.

The solution seems to be to put the image_end_marker into a different
object file so that the compiler cannot play any tricks to resolve
the address internally in the object file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Fix output format for aarch64. Also, relocation fixup symbols are in
rela section rather than rel section.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The ld_var solves the issue that when compiled with -pie the linker
provided variables are all 0x0. This mechanism however refuses to
compile with aarch64 support.

This patch replaces the ld_var mechanism with a nice little trick
learned from U-Boot: Instead of using linker provided variables
directly with "__bss_start = ." we put a zero size array into
a separate section and use the address of that array instead of
the linker variable. This properly works before relocation.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ld_var is going to be removed, cope without it. In the PBL image
we want to get the location after the binary to the place where
the compressed image is located. To do this Put a variable at
the very end of the binary, get it's location and add an offset.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This file originates in Linux.  Linux has it under include/linux/
directory since commit dccd2304cc90.
Let's move it to the same place as well in barebox.

This commit was generated by the following commands:

  find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:'
  git mv include/sizes.h include/linux/

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

It's often useful to get some information about a barebox image
before starting or flashing it. This patch introduces barebox
Image MetaData (IMD). When enabled a barebox image will contain
a list of tags containing the desired information. We have tags
for:

- the barebox release (2014.07.0-00160-g035de50-dirty)
- the build timestamp (#741 Mon Jul 28 15:08:54 CEST 2014)
- the board model the image is intended for
- the device tree toplevel compatible property

Also there is an additional generic key-value store which stores
parameters for which no dedicated tag exists. In this patch it
is used for the memory size an image supports.

Since there is no fixed offset in a barebox image which can be
used for storing the information, the metadata is stored somewhere
in the image and found by iterating over the image. This works
for most image types, but obviously not for SoC images which are
encoded or encrypted in some way.

There is a 'imd' tool compiled from the same sources for barebox,
for the compile host and for the target, so the metadata information
is available whereever needed.

For device tree boards the model and of_compatible tags are automatically
generated.

Example output of the imd tool for a Phytec phyFLEX image:

build: #889 Wed Jul 30 16:08:54 CEST 2014
release: 2014.07.0-00167-g6b2070d-dirty
parameter: memsize=1024
of_compatible: phytec,imx6x-pbab01 phytec,imx6dl-pfla02 fsl,imx6dl
model: Phytec phyFLEX-i.MX6 Duallite Carrier-Board

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The FSF address has changed; The FSF site says that
address is

  Free Software Foundation
  51 Franklin Street, Fifth Floor
  Boston, MA 02110-1301
  USA

(see http://www.fsf.org/about/contact/)

Instead of updating it each time the address changes,
just drop it completely treewide.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This allows to load all the lowlevel init code, including the
uncompressor, inside SRAM and not just the bare init part. This is
useful when pbl is used as a first-stage bootloader but is loaded by an
external firmware.

Signed-off-by: David Vincent <freesilicon@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

TEXT_BASE - SZ_2M is only used for non relocable pbl images.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

In the upcoming multi image build process we will cat images together.
To find the concatenated image we need to reliably find the end of the
current binary. This adds a dummy section at the end of a pbl binary.
Its only purpose is to mark the end of the image. The multi image
patches will add something to this section so that it doesn't get
discarded by the linker.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Since the pbl linker script can be reused by the upcoming multi image
build process move it to a common place. Also remove ENTRY() from the
linker script and instead add the -e option to the linker. This makes
the entrypoint configurable.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>