MMC: IMX: Reset MMC_BOOT register after controller reset. ...

This helps with EMMC detection when booting from EMMC directly.
Taken from u-boot.

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MCI: imx-esdhc: implement workaround for errata ENGcm12360 ...

At least i.MX53 has errata ENGcm12360:

Occurs when a pending command which issues busy is completed.
For a command with R1b response, the proper software sequence
is to poll the DLA for R1b commands to determine busy
state completion. The DLA polling is not working properly for
the ESDHC module. This is relevant for all eSDHC ports (eSDHC1-4 ports)

DLA bit in PRSSTAT register cannot be
polled to wait for busy state completion.

Updated block guide to reflect that DLA is not applicable to detect
busy state, instead, should poll bit 24 in PRSSTAT register (DLSL[0] bit)
to check that wait busy state is over.

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: sdhci: fix IRQSTAT_DMAE bit shift ...

According to the SD Host Controller Specification Version 3.00, the ADMA error
status bit is on the wrong bit. Fix this.

While at it, add the missing standard error status bits.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci i.MX esdhc: Fix clock divider calculation ...

This updates the i.MX esdhc divider settings to FSLs U-Boot.
Current timings work fine for SD cards, but not for eMMC.
Although the calculation is fine according to the datasheet and reading from
eMMC works, writing is broken. Atleast on i.MX53/tqma53.
With this patch the result is the same, but uses different divider values to
achieve it.

While at it, replace the udelay with a busy-loop.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc: factor out common sdhci registers ...

This gives the SDHCI specific registers a common name and moves
them to a separate file for use by other SDHCI like drivers.

The SDHCI spec has some 16bit and 8bit registers. The i.MX accesses
these as 32bit registers. These register defines now are named after
the SDHCI registers they combine into one, for example:

SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL

is the 32bit version of the SDHCI registers HOST_CONTROL, POWER_CONTROL
and BLOCK_GAP_CONTROL.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>