Move clk code from 'mach-imx' to 'drivers' to keep the code tree
structure closer to that of analogous one from Linux kernel and,
arguably although subjective, to keep 'mach-imx' less cluttered.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Some boards or SoCs need the SRC_SCR[WARM_RESET_ENABLE] bit cleared,
otherwise they won't come up after a watchdog reset. This was observed
on one i.MX6ul based custom board. The Linux Kernel does the same since
2012: 0575fb7 ARM: 7198/1: arm/imx6: add restart support for imx6q.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Nearly identical to Linux-4.8 clock support, only some unnecessary
clocks skipped.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Some i.MX53 want to setup the SDRAM from C code rather than
from DCD tables. The image size for these boards is limited
to the internal SRAM size. To overcome this limitation for
i.MX53 boards booting from NAND implement an xload mechanism
to load only the PBL to SRAM and let barebox load the rest
of the image itself after SDRAM has been initialized.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add PBL xload code to load an image from SPI NOR flash. Currently implemented
for i.MX6.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

As boot.c now contains code for the pbl compile compile it there
awell. While at it move esdctl.c to obj-pbl-y.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Conflicts:
	common/Kconfig

The code can be used on i.MX28 aswell, so move it to a common place.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This commit add a very basic code to allow Barebox to be booted from
IRAM. Given that the amount of IRAM on most i.MX variants is
insufficient to contain a copy of Barebox with any reasonable degree
of functionality this code uses IRAM only as a temporary location and
eventually bootstraps from DRAM. But the presense of the intermediate
IRAM-only stage allows to add provisions to test the area of DRAM that
Barebox would be using to facilitate various testing scenarious.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This adds support for two gates from can only exclusively be enabled.
Based on the corresponding Linux code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add some cpu type defines and clock support. The clock support
is very different from other i.MX variants, so it's a separate
file, like done in the kernel.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Based on kernel clk-gate2 and barebox clk-gate implementations.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Enables all relevant errata workarounds for the
i.MX6 SoC.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The only functionality at the moment is to register a MAC Address for
an ethernet device.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

imx_silicon_revision() can't be used from early init context, so
use imx51_silicon_revision() instead.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Conflicts:
	arch/arm/mach-imx/Makefile

For consistency reasons.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

For consistency reasons.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This switches the iomux-v3 (found on i.MX25,35,51,53,6) to pinctrl
support. The old SoC specific API is kept for compatibility. The
pinctrl devicetree support is enabled automatically when OFDEVICE
support is available.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Fix realq7 compilation

The external NAND boot code currently does not handle bad blocks
correctly on 2k NAND flashes. This patch adds a barebox_update
handler for external NAND boot which embeds a Bad block table in
the flashed image. The boot code will skip bad blocks found in
this bad block table then.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This adds support for the various DDR calibration functions in the
i.MX6 MMDC.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Most i.MX boards can use the imx*_barebox_entry functions. The remaining
(i.MX21, i.MX6) use hardcoded base addresses.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>