For all users fix or add the error check.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This adds a clk_gate_flags argument to clock gate creation functions
to allow the introduction of new clock gate modifiers.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

since the switch to common clock, ethernet driver doesn't works and
and access to the network leads to :
eth0: Read MDIO failed...
unable to handle NULL pointer dereference at address 0x000000c7

The problem is that bit 31 (SLEEP) of register HW_CLKCTRL_ENET is kept
to its default value (1) which means : "put Ethernet block in sleep mode.
CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and CLK_ENET0(1)_TX are gated off.
Ethernet can be wakeup remotely in sleep mode"
In that case the FEC don't get its clock.

This patch fix the problem by toggling this bit when FEC's clock is
enabled.

Tested on i.MX28EVK.

Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

When changing the rates of the ssp clocks we have to poll the
busy bit, but only when they are enabled. The current code can
not check this properly since the gates are registered as children
of the dividers. This has the effect that when the gate is disabled
the busy bit will be set forever resulting in a freezed system.

Fix this by making the gates parents of the dividers which allows
clk_is_enabled to return the correct result.

The Kernel has the same problem, but here the busy polling is
limited to 10ms, so probably noone noticed this.

The datasheet mentions that the ssp dividers shall only be changed
when the clocks are enabled. The kernel and barebox currently ignore
this. I don't know what effect violating this rule has.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

This adds support for the i.MX23 and i.MX28 clock modules. This mostly is
a copy from the kernel.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>