pinctrl: add driver for STM32 GPIO and pin multiplexer ...

This adds driver support for the 12 GPIO banks on the STM32MP157.
As they are accessible to both the Cortex-A cores as well as the Cortex-M
core, modifications to these are protected by a hardware spinlock
and clocks are enabled/disabled as required.

All register fiddling done by the driver is collected in <soc/stm32/gpio.h>,
so future PBL code may make use of it as well to chainload barebox proper.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: stm32mp1: rename to stm32mp ...

Serial and clk driver both depend on CONFIG_ARCH_STM32MP1,
so either the Kconfig symbol or their depend needs to change.

Patches posted by the vendor to Linux, U-Boot and their BSP
Yocto-Layer speak of a STM32MP-Family of which the STM32MP1
is the first series, thus rename the arch by dropping the 1.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: psci: factor out of_psci_fixup() to separate file ...

of_psci_fixup() can be used by code which doesn't use the barebox
psci implementation, but provides its own PSCI compatible firmware.
Factor it out to a separate file to compile it independently of the
barebox PSCI implementation.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/stm32'

Merge branch 'for-next/misc'

treewide: surround Kconfig file paths with double quotes ...

Based on Linux commit 8636a1f

This will be needed when you sync Kconfig with Linux 5.0 or later.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: Add Layerscape clk support ...

This adds support for the clock controller found on Layerscape
SoCs. This is mostly an adoption of the corresponding Linux
driver. This is tested on the LS1046a SoC. Other ARM based Layerscape
SoCs should work aswell, support for the PowerPC based SoCs has
been removed.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add basic Layerscape support ...

This adds basic Layerscape support:

- Makefile/Kconfig
- Register maps
- errata workarounds

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add initial STM32MP1 support ...

This adds initial STMicroelectronics MP1 support along with support
for the DK2 devel board. Only very basic support:

- UART
- SDRAM memory base/size
- No 1st stage support

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

firmware-zynqmp: port from linux ...

Port Xilinx Zynq MPSoC Firmware layer driver from linux.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynqmp: select macb driver ...

macb supports Xilinx ZynqMP GEM, so select HAS_MACB by default.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle1988@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynqmp: add support for Xilinx ZCU104 board ...

Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP)
and the Xilinx ZCU104 board.

Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL)
already took care of initializing the RAM. Also for debug_ll, the UART
is expected to be already setup correctly. Thus, you have to add the
Barebox binary to a boot image as described in "Chapter 11: Boot and
Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual".

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

kconfig: include common Kconfig files from top-level Kconfig ...

Based on this linux kernel commit:

> commit 1572497
> Author: Christoph Hellwig <hch@lst.de>
> Date:   Tue Jul 31 13:39:30 2018 +0200
>
>     kconfig: include common Kconfig files from top-level Kconfig

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/socfpga'

ARM: socfpga: Arria10: support programming FPGA in PBL ...

Some Arria10 boards don't have the FPGA programmed externally.
Instead barebox needs to do that. As the Arria10 has the SDRAM
controller in the FPGA, the first thing we need to do is,
configure the FPGA before the SDRAM can even be used.

It works like this:
  1. boot ROM fetches the PBL from MMC
  2. read the MBR from MMC (this depends on the setup done by the boot ROM)
  3. read the Bitstream from the MMC and program the FPGA
  4. re-read the barebox image from MMC, this time with the full barebox
     that is appended to the PBL
  5. jump into the full barebox

Only supported boot device is eMMC.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add code to support SMCCC on AArch64 ...

Port SMCCC code from Linux kernel. To accomodate that:

  - Introduce CONFIG_ARM_SMCCC, to allow enabling the code
    independent of CONFIG_ARM_SECURE_MONITOR

  - Bring <linux/arm-smccc.h> in

  - Add necessary constants to arch/arm/asm-offsets.c

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/misc'

scripts: create a separate section for host tools ...

This allows to enable host tools even if they are not needed for the
current configuration to improve compile coverage and simplify packaging
these tools. The conversion doesn't cover all tools available but can be
extended later.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: lib64: Make string functions aware of MMU configuration ...

Optimized version of memset() in memset.S if called as:

    memset(foo, 0, size)

will try to explicitly zero out data cache with:

    dc	zva, dst

which will result in Alignement Exception (DABT) if MMU is not
enabled.

For more info see:

    - C4.4.8 "DC ZVA, Data Cache Zero by VA"
    - D5.2.8 "The effects of disabling a stage of address translation"

in "ARM Architecture Reference Manual. ARMv8, for ARMv8-A architecture
profile"

In similar vein, using optimized version of memcpy() could lead to a
unaligned 16-byte write (using 'stp'), which is not allowed for
Device-nGnRnE type of memory (see D5.2.8) and would liead to
Alignement Exception.

To fix both problems expose non-optimized and optimzied versions of
the function and created a wrapper to dispatch the call to either one
based on if MMU is enabled or not.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add builtin firmware support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[andrew.smirnov@gmail.com: Add dummy.o in case directory is empty]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: aarch64: hide some config options ...

EABI and ATAGS have no meaning on aarch64, so hide the options from the
user.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: For relocatable image force TEXT_BASE 0x0 ...

Nothing else should be used for the relocatable image case, so
force TEXT_BASE to 0x0 and do not show it in the menu.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: add arria10 support ...

Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that
is already supported in barebox.
Both a the same in some parts, but totaly different in
others. Most of the hardware blocks are the same in the
SoC parts. The OCRAM is larger on the Arria10 and the
SDRAM controller is different.
The serial core only supports 32bit accesses (different to
the 8bit accesses on the Cyclone5).

As Arria10 has 256KB of OCRAM, it is possible to fit a larger
barebox (and/or use PBL) instead of the two stage bootprocess
used on the Cyclone5 and its 64KB OCRAM.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/misc'

ARM: mvebu: remove obsolete select ...

This is a user choice now and has been removed for all other boards in commit
790980bf18af ("Make generic default environment type a use choice").

Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

poweroff: Allow to register poweroff handlers ...

Allow to register handlers for poweroff. This allows to have multiple
poweroff implementations in a single binary. The implementation is close
to the restart handlers.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

at91sam9x5ek: Convert to mult-image build ...

Convert AT91SAM9X5-EK board code to multi-image build process, similar
to how majority of i.MX board code is built.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: at91: Port at91 DT clock code ...

Port at91 DT clock code from Linux 4.9-rc3.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/rpi'

Merge branch 'for-next/mvebu'