PCI: dwc: Enable iATU unroll for endpoint too ...

Port of Linux commit a9f4c2d

    iatu_unroll_enabled flag is set only for Designware in host mode.

    However iATU unroll can be applicable for endpoint mode too. Set
    iatu_unroll_enabled flag in dw_pcie_setup() which is common for
    both host mode and endpoint mode.

    Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Don't hard-code DBI/ATU offset ...

Port of Linux commit 6d6b05e

    The DWC PCIe core contains various separate register spaces: DBI, DBI2,
    ATU, DMA, etc. The relationship between the addresses of these register
    spaces is entirely determined by the implementation of the IP block, not
    by the IP block design itself. Hence, the DWC driver must not make
    assumptions that one register space can be accessed at a fixed offset from
    any other register space. To avoid such assumptions, introduce an
    explicit/separate register pointer for the ATU register space. In
    particular, the current assumption is not valid for NVIDIA's T194 SoC.

    The ATU register space is only used on systems that require unrolled ATU
    access. This property is detected at run-time for host controllers, and
    when this is detected, this patch provides a default value for atu_base
    that matches the previous assumption re: register layout. An alternative
    would be to update all drivers for HW that requires unrolled access to
    explicitly set atu_base. However, it's hard to tell which drivers would
    require atu_base to be set. The unrolled property is not detected for
    endpoint systems, and so any endpoint driver that requires unrolled access
    must explicitly set the iatu_unroll_enabled flag (none do at present), and
    so a check is added to require the driver to also set atu_base while at
    it.

    Signed-off-by: Stephen Warren <swarren@nvidia.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
    Acked-by: Vidya Sagar <vidyas@nvidia.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/pci'

Merge branch 'for-next/misc'

PCI: dwc: Fix pointer width cast problem ...

Casting to u32 works well on 32-bit builds, but causes problem when
compiled on 64-bit machines. Switch it to cast to "unsigned long", so
that it would have appropriate width in both cases.

While at it, replace explicit casts to void * with IOMEM.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

treewide: Remove trailing whitespaces and tabs ...

Just a cleanup over barebox tree

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Consify pci_ops in struct pci_controller ...

Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Assume 1:1 mapping if .res_start callback is NULL ...

Save a bit of no-op boilerplate by converting pci_iomap() to treat
absense of .res_start callback as an indicator that 1:1 mapping is
being used.

Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Small computation improvement ...

Port of a Linux commit 6995de2

  Replace a division by 2 operation for a right shift rotation of 1 bit.

  Probably any recent and decent compiler does this kind of substitution
  in order to improve code performance. Nevertheless it's a coding good
  practice whenever there is a division / multiplication by multiple of 2
  to replace it by the equivalent operation in this case, the shift
  rotation.

  Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Fix enumeration end when reaching root subordinate ...

Port of a Linux commit c2deae4

  The subordinate value indicates the highest bus number which can be
  reached downstream though a certain device.

  Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
  parent")
  ensures that downstream devices cannot assign busnumbers higher than the
  upstream device subordinate number, which was indeed illogical.

  By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
  value of 0x01.

  Due to this combined with above commit, enumeration stops digging deeper
  downstream as soon as bus num 0x01 has been assigned, which is always
  the case for a bridge device.

  This results in all devices behind a bridge bus to remain undetected, as
  these would be connected to bus 0x02 or higher.

  Fix this by initializing the RC to a subordinate value of 0xff, which is
  not altering hardware behaviour in any way, but informs probing
  function pci_scan_bridge() later on which reads this value back from
  register.

  Following nasty errors during boot are also fixed by this:

  [    0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff]
  under [bus 01] (conflicts with (null) [bus 01])
  ...
  [    0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge
  0000:01 [bus 01]
  ...
  [    0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge
  0000:01 [bus 01]
  ...
  [    0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge
  0000:01 [bus 01]
  [    0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to
  05
  [    0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05]
  under [bus 01] (conflicts with (null) [bus 01])
  [    0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind
  bridge 0000:01 [bus 01]

  Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in
  parent")
  Tested-by: Niklas Cassel <niklas.cassel@axis.com>
  Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
  Tested-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
  Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
  Acked-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: <stable@vger.kernel.org> # 4.15
  Cc: Binghui Wang <wangbinghui@hisilicon.com>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Jesper Nilsson <jesper.nilsson@axis.com>
  Cc: Jianguo Sun <sunjianguo1@huawei.com>
  Cc: Jingoo Han <jingoohan1@gmail.com>
  Cc: Kishon Vijay Abraham I <kishon@ti.com>
  Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
  Cc: Minghuan Lian <minghuan.Lian@freescale.com>
  Cc: Mingkai Hu <mingkai.hu@freescale.com>
  Cc: Murali Karicheri <m-karicheri2@ti.com>
  Cc: Pratyush Anand <pratyush.anand@gmail.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>
  Cc: Roy Zang <tie-fei.zang@freescale.com>
  Cc: Shawn Guo <shawn.guo@linaro.org>
  Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
  Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  Cc: Xiaowei Song <songxiaowei@hisilicon.com>
  Cc: Zhou Wang <wangzhou1@hisilicon.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates ...

Port of a Linux commit d91dfe5

  dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt
  Pin registers, but the fixes don't actually work because these registers
  are read-only.

  Enable write permission before updating the Class Code and Interrupt
  Pin.

  Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Roy Zang <tie-fei.zang@freescale.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Handle ->host_init() failures ...

Port of a Linux commit 4a30176

  In several dwc-based drivers, ->host_init() can fail, so make sure to
  propagate and handle this to avoid continuing operation of a driver or
  hardware in an invalid state.

  Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Replace lower into upper case characters ...

Port of a Linux commit b4a8a51

  Replace of all initial lowercase character in comments and debug messages
  to uppercase to maintain coherence.

  Fix messages coherence within the DesignWare driver.

  Fix code style on dw_pcie_irq_domain_free() function.

  Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate ...

Port of a Linux commit 8cfab3c

  Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license.

  Remove the boilerplate GPL version 2 language, relying on the assertion in
  b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
  files with no license") that the SPDX identifier may be used instead of the
  full boilerplate text.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Fix typos and whitespace errors ...

Port of a Linux commit 96291d5

  Fix various typos and whitespace errors:

    s/Synopsis/Synopsys/
    s/Designware/DesignWare/
    s/Keystine/Keystone/
    s/gpio/GPIO/
    s/pcie/PCIe/
    s/phy/PHY/
    s/confgiruation/configuration/

  No functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Split pcie-designware.c into host and core files ...

Port of a Linux commit feb85d9

  Split pcie-designware.c into pcie-designware-host.c that contains the host
  specific parts of the driver and pcie-designware.c that contains the parts
  used by both host driver and endpoint driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>