Avoid build error on "config SPI" is y ...

In case he configures with make ARCH=x85 menuconfig,
config SPI will be set to "y". And he will got an error on spi.h.

Signed-off-by: Masaki Muranaka <monaka@monami-ya.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: pbl: Always call pbl make ...

We always must decend into the pbl build. Otherwise it doesn't get
rebuilt if only sourcefiles from the pbl are changed.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX53 vincell: Fix lowlevel startup ...

This is a i.MX53 board, not i.MX51.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX53: tqma53: fix console entry ...

The default baseboard for the tqma53 (MBa53) uses UART2 for debug console.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: Add cmd to generate zynq image ...

Add a command to generate the zynq image instead of generating it
directly. This causes a rebuild exactly when necessary and prints
a "ZYNQ-IMG" to the commandline during compilation.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: pbl: fix make dependencies ...

The pbl used 'zbarebox.bin' as target instead of the real file. This
lead to strange effects that the images depending on zbarebox.bin were
only built every second time. This uses the full path as target.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: invalidate data caches during early init ...

Some SoCs come up with invalid entries in the data cache. This can
lead to memory corruption when we enable them later, so invalidate
the caches early.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Lucas Stach <l.stach@pengutronix.de>

ARM v7: added v7_mmu_cache_invalidate() ...

At least the iMX6 boot rom seems to jump into barebox with a non
invalidated d-cache which causes data corruption when
v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides
stack or other valid data.

That's why the cache must be invalided for this processors explicitly
(e.g. in barebox_arm_reset_vector()).  Operation differs from flush only
in one instruction so that patch modifies the existing
v7_mmu_cache_flush() function slightly by adding an optional argument.

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM v7: v7_mmu_cache_flush(): do not restore r0-r3 (minor optimization) ...

Registers 'r0' till 'r3' are scratch registers and do not need to be
restored.

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: properly init alignment trap bit ...

On ARMv7 the intention is to disable the alignment trap to be able to
use hardware assisted unaligned load/stores. Fix the init to do the
right thing.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: fix the memset fix ...

From Kernel commit 418df63a ARM: 7670/1: fix the memset fix

| Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
| recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
| with the memset return value.  However the memset itself became broken
| by that patch for misaligned pointers.
|
| This fixes the above by branching over the entry code from the
| misaligned fixup code to avoid reloading the original pointer.
|
| Also, because the function entry alignment is wrong in the Thumb mode
| compilation, that fixup code is moved to the end.
|
| While at it, the entry instructions are slightly reworked to help dual
| issue pipelines.
|
| Signed-off-by: Nicolas Pitre <nico@linaro.org>
| Tested-by: Alexander Holler <holler@ahsoftware.de>
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM v7: fix mmu-off operation ...

Although conclusions in 50d1b2d "ARM
v7: Fix register corruption in v7_mmu_cache_off" are correct, the
implemented fix is not complete because the following failure can
happen:

1. d-cache contains the cache line around 'sp'

2. v7_mmu_cache_off() disables cache

3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack

4. v7_mmu_cache_flush() flushes d-cache and can override stack written
   by step 3.

5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which
   might be random data now.

Patch avoids step 3 which is easy because 'lr' is never modified by the
function.  By using the 'r12' scratch register instead of 'r10', the
whole initial 'push' can be avoided.

Patch moves also the 'DMB' operation so that it is executed after data
has been pushed on stack.

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: ccmx51: Another fix SDRAM size detection ...

For CCMX51-boards now we do not use ESDCTL, but actual command for
adding memory is missing. This patch fix this issue.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: remove unused clkdev.h ...

See also:

  commit eb84709
  Author: Sascha Hauer <s.hauer@pengutronix.de>
  Date:   Mon Mar 25 15:18:38 2013 +0100

      clk: remove unused __clk_[get|put]

      This is some unused code resulting from copying stuff from
      the kernel. Remove it.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MXS: fix SoC detecting ...

The missing 'break' statement lets look an i.MX23 like an i.MX28.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: ccxmx51: detect SDRAM size by board id ...

This partly reverts:

commit 697e02b
Author: Alexander Shiyan <shc_work@mail.ru>
Date:   Tue Jan 22 15:08:31 2013 +0400

    ARM: ccmx51: Remove SDRAM size settings

    This patch removes SDRAM memory size setting from board due
    to auto detect last one by ESDCTL.

    Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
    Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The board originally configured the SDRAM controller for the
maximum size and detected the usable SDRAM size by reading the
board id. This became broken after switching to automatic SDRAM
size detection by reading back ESDCTL values.

This patch brings back the old behaviour.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: Allow disabling SDRAM autodetection ...

Some boards setup more memory than they actually have. The real memory
size can then be detected later for example by reading a board id.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

sama5d3xek: correct rootfs nand partition ...

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX31 pcm037: fix erroneous IOMUX GPR setup in pcm037_usb_init() ...

In commit ad09b59 "ARM i.MX31: give
register base addresses a proper MX31_ prefix", the IOMUX GPR setup
to enable USBH2 was replaced with an incorrect source register.
Instead of reading the GPR register, USBOTG HWHOST is used as rmw source,
which contains 0x10020001.
Beside the intended GPR[11] setup ("Enable USBH2 signals on AudioPort 3 and
AudioPort6"), this erroneously also sets
	GPR[28] enable USBOTG loopback
	GPR[17] override DSR_DCE1 with USBOTG_DATA4
	GPR[0]  select FIR DMA requests instead of UART2 DMA

Beside breaking UART2, it probably also broke some UART1 and USB OTG setups.
Fix this and replace the address with the appropriate defines.

Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX31: cleanup MX31_ prefix: fix leftover IOMUXC_BASE defines ...

The prefix/cleanup series
	ad09b59
	a8c6359
	4c53af0
missed a few unprefixed IOMUXC_BASE define users. Fix these.

Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/tegra'

Merge branch 'for-next/remove-config-h'

Merge branch 'for-next/param' ...

Conflicts:
	drivers/mci/mci-core.c

Merge branch 'for-next/omap'

Merge branch 'for-next/of' ...

Conflicts:
	arch/arm/mach-imx/Makefile

Merge branch 'for-next/misc'

Merge branch 'for-next/imx'

Merge branch 'for-next/gpio'

Merge branch 'for-next/atmel'

ARM: ccmx51js: Add support for USB Host1 ...

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>