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History for barebox / arch

2014-08-01	c1016b2 Browse files » ARM: AM3355x: Update defconfig ... Most diffstat comes from refreshing the config. The only real change is that the NAND xload update handler is enabled now. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 1 Aug 2014
	6efdb42 Browse files » ARM: phyCORE-am335x: Add support for more SDRAM configurations ... This adds support for 256MB and 128MB RAM configurations of the phyCORE-AM335x. This is done as new images. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 1 Aug 2014
	bcf7cde Browse files » ARM: phyCORE-am335x: read back SDRAM controller settings ... - use am335x_barebox_entry() to remove the need for hardcoded SDRAM size - remove hardcoded memory settings from device tree since there are different memory sizes available for this board. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 1 Aug 2014
	61cbf21 Browse files » ARM: AM33xx: Add SDRAM size detection ... This adds a function which reads back the SDRAM controller settings. This is used in a AM33xx specific barebox entry function and a SDRAM driver which registers a SDRAM memory bank. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 1 Aug 2014
	b549a26 Browse files » watchdog: add minimal jz4740 driver ... Also move reset_cpu() for jz4755 SoC from platform code into the new driver code. At the moment mach-xburst lacks clk support so jz4740 watchdog driver looks like a template. We can improve jz4740 watchdog driver later after adding clk support. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 31 Jul 2014 Sascha Hauer committed on 1 Aug 2014
	70e769a Browse files » ppc: DA923RC: 16-bit Product Data EEPROM read access ... Change Product Data validity checking to ensure that support can be provided for 8-bit and 16-bit EEPROM devices. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Renaud Barbier authored on 31 Jul 2014 Sascha Hauer committed on 1 Aug 2014
2014-07-31	db32b11 Browse files » ARM: am335x Phytec phyCORE: Enable ethernet ... With an update of the am33xx.dtsi (commit 9313920df6) the mdio and mac nodes are not enabled on default any more. Enable them explicit in the board dts now. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Teresa Gámez authored on 9 Jul 2014 Sascha Hauer committed on 31 Jul 2014
	4ab73e2 Browse files » sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot ... The configuration for NAND has been aligned with values from U-Boot and completed with TIMINGS initialization Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Matteo Fortini authored on 21 Jul 2014 Sascha Hauer committed on 31 Jul 2014
	322f0ef Browse files » sama5d3x: fix HSMC MODE register offset and add TIMINGS register ... As stated in section 29.19.35 of SAMA5D3 Series Datasheet, MODE register has offset 0x10 and at offset 0x0C there is a TIMINGS register. Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Matteo Fortini authored on 21 Jul 2014 Sascha Hauer committed on 31 Jul 2014
	45efb46 Browse files » MIPS: ritmix-rzx50_defconfig: enable LED-related stuff ... Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 30 Jul 2014 Sascha Hauer committed on 31 Jul 2014
	e928554 Browse files » MIPS: dts: rzx50.dts: add LCD backlight ... Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 30 Jul 2014 Sascha Hauer committed on 31 Jul 2014
	5a9ba98 Browse files » pci: mvebu: Add PCIe driver ... This adds a PCI driver for the controllers found on Marvell MVEBU SoCs. Besides the functional driver itself, it also adds SoC specific PHY setup required for PCIe. Currently, only Armada 370 is fully supported. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 30 Jul 2014 Sascha Hauer committed on 31 Jul 2014
	7587a04 Browse files » ARM: mvebu: armada-370-xp: disable MBUS error propagation ... Accessing MBUS windows not backed-up by e.g. PCIe devices will hang the SoC. Disable MBUS error propagation back to CPU allows to read 0xffffffff instead of hanging the SoC. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 30 Jul 2014 Sascha Hauer committed on 31 Jul 2014
2014-07-29	0e2111d Browse files » ARM: DIGIC: add Canon PowerShot A1100 IS support ... Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 28 Jul 2014 Sascha Hauer committed on 29 Jul 2014
	f1fb740 Browse files » ARM: add very initial support for Canon DIGIC chips ... Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 28 Jul 2014 Sascha Hauer committed on 29 Jul 2014
	420ca0b Browse files » ARM: add ARM946E-S CPU type ... ARM946E-S is used in the DIGIC family SoCs. ARM946E-S core supports ARMv5TE and has Cache & MPU. Linux kernel uses ARMv4 MPU cache routines for ARM946E-S core. E.g. see linux.git/boot/compressed/head.S: .word 0x41009400 @ ARM94x .word 0xff00ff00 W(b) __armv4_mpu_cache_on W(b) __armv4_mpu_cache_off W(b) __armv4_mpu_cache_flush So select CPU_32v4T for ARM946E-S despite of ARMv5TE support. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 28 Jul 2014 Sascha Hauer committed on 29 Jul 2014
	8a0fe27 Browse files » ARM: at91: clock: fix the pllb checking ... On at91sam9n12 soc, it has pllb, while on sama5d3 soc, it doesn't has pllb. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Bo Shen authored on 29 Jul 2014 Sascha Hauer committed on 29 Jul 2014
2014-07-28	d840f17 Browse files » ppc: minimal Freescale P1010RDB board support ... This is a limited board support for the Freescale P1010RDB. The board boots from NOR and output the prompt to the serial port at 115200 bauds. All 3 Ethernet ports are supported by the gianfar driver. I2C devices are accessible on both bus and the memory is initialised by the 85xx DDR driver. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Renaud Barbier authored on 25 Jul 2014 Sascha Hauer committed on 28 Jul 2014
	52aec0e Browse files » ppc: Freescale P1010 SoC support ... Add support for the Freescale P1010 including errata for this CPU, SoC frequency calculation and GPIO settings. The mpc85xx configuration options file is re-ordered to facilitate board option selection. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Renaud Barbier authored on 25 Jul 2014 Sascha Hauer committed on 28 Jul 2014
	7e2d924 Browse files » ppc: Freescale P1010 headers ... Add a minimal Integrated Flash Controller header file and new definitions to support the P1010 SOC. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Renaud Barbier authored on 25 Jul 2014 Sascha Hauer committed on 28 Jul 2014
	7e1e8aa Browse files » ppc: 85xx: CCSRBAR mapping moved to start-up code. ... Move the configuration, control and status register base address (CCSRBAR) relocation to the start-up processing. This addresses TLB faults found during testing on the Freescale P1010RDB and also matches the current U-Boot functionality. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Renaud Barbier authored on 25 Jul 2014 Sascha Hauer committed on 28 Jul 2014
2014-07-25	0992c07 Browse files » ARM: mvebu: add fixup for directly attached memory ... On Marvell MVEBU SoCs memory size is set up by BootROM and can be read from SoC's RAM controller. With early DT fixups available, set corresponding DT node to reflect accessible amount of directly attached RAM. This patch also removes non-DT call to arm_add_mem_device to silence a warning about request_region conflict due to adding a mem device twice. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 23 Jul 2014 Sascha Hauer committed on 25 Jul 2014
	c148e36 Browse files » ARM: dts: mvebu: remove mbus ranges overwrite ... With proper DT fixup in place, we can now remove the overwrite of mbus ranges in Armada 370 Mirabox and Armada XP Openblocks AX3. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 23 Jul 2014 Sascha Hauer committed on 25 Jul 2014
	a9acc23 Browse files » ARM: mvebu: add register remap for mbus ids ... For each supported MVEBU SoC, add the corresponding remapped registers to fix them up in provided DTBs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 23 Jul 2014 Sascha Hauer committed on 25 Jul 2014
	5f1c610 Browse files » ARM: execute OF fixups early ... Device trees can be passed by primary boot loader or appended to barebox binary. Unfortunately, before probing devices from such a device tree, no fixup can be applied. Add a call to of_fix_tree() right before probing devices to catch some very early fixups. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 23 Jul 2014 Sascha Hauer committed on 25 Jul 2014
2014-07-24	d73ad85 Browse files » ARM: i.MX5: internal NAND update: simplify code ... Allocate space for the resulting image (FCB+DBBT+Firmware) in imx_bbu_internal_v2_write_nand_dbbt() instead of its caller to make the code simpler. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 24 Jul 2014
	55eb21d Browse files » ARM: i.MX5: internal NAND update: Use variables for some constants ... Instead oof using the same constants multiple times use a variable to make the meaning of the constants clear. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 24 Jul 2014
	304ef1f Browse files » ARM: i.MX5: internal NAND update: Fix firmware start page for internal nand boot ... Documentation clearly states that the FCB at offset 0x68 has to contain the start page of the firmware. In our case this was set to 0x0. I don't know how this could ever work, but it did, at least until: 15ee301 ARM: i.MX: bbu-internal: optionally use DCD data from image Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 24 Jul 2014
	b49b0d4 Browse files » ARM: i.MX5: internal NAND update: Use variable for pre_image_size ... We have the hardcoded value 0x8000 for the space needed for FCB and DBBT in several places. Use a variable instead and initialize it correctly with 12 * meminfo.writesize (which is in fact 0x6000 for 2k pagesize). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 24 Jul 2014
2014-07-23	d0e0a97 Browse files » pinctrl: mvebu: add pinctrl driver for Armada XP ... This adds a pinctrl driver for pin muxing on Marvell Armada XP. The driver is ported from Linux and modified to fit on Barebox's common mvebu pinctrl driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 22 Jul 2014 Sascha Hauer committed on 23 Jul 2014