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History for barebox / drivers / mtd

2015-12-08	d10a05b Browse files » Merge branch 'for-next/mtd' Sascha Hauer committed on 8 Dec 2015
2015-11-23	770c1ef Browse files » mtd: core: initialize retlen in mtd_write() ... Some mtd drivers like the spi-nor driver do not assign a value to the retlen pointer but instead only add the bytes written to retlen. Users of mtd_write expect the variable to be initialized by the mtd core though, so we have to do it in mtd_write(). The same is done in mtd_read already. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 23 Nov 2015
	f01b562 Browse files » mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U ... This adds optimized timings for Samsung K9K8G08U 1Gb NAND flash. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	131d5b5 Browse files » mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP ... Marvell PXA3xx and Armada 370/XP share the same NAND controller IP with some minor differences. With support for controller IP v2, now allow to build the driver on Armada 370/XP. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	7c6e711 Browse files » mtd: nand_mrvl_nfc: Add support for NDCB3 register ... Newer versions of PXA3xx NAND controller support a 4th Command Buffer register. Add the required HWFLAGS and additional write to NDCB0. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	87bddaf Browse files » mtd: nand_mrvl_nfc: Add support for HW BCH ECC ... Add support for HW BCH ECC for those HW versions that support it. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	f7d39e1 Browse files » mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC ... Add support for 8bit HW ECC modes supported by later IP versions. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	624bea7 Browse files » mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECC ... Add support for 4bit HW ECC modes supported by later IP versions. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	4647cb1 Browse files » mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions ... Marvell PXA3xx NAND flash controller IP has been reused in later SoCs with additional HW features. Add HW BCH ECC as the first known HW difference. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	fa8ece6 Browse files » mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths ... Newer versions of Marvell PXA3xx NFC also support BCH and therefore higher ECC strengths than 1. Prepare for different ECC strength by factoring out ECC init into separate functions by strength. Also, add a new host variable that indicates BCH ECC. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	75783fa Browse files » mtd: nand_mrvl_nfc: Get ecc parameters from DT ... With DT helpers for ECC step size and strength, now use them on Marvell NAND driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	0ba6906 Browse files » mtd: nand_mrvl_nfc: Fix num-cs property parsing ... The "num-cs" property does not encode flashes CS line but number of available CS signals. Fix wrong property parsing to ->cs by adding proper ->num_cs variable to host struct. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	81a0cfc Browse files » mtd: nand_mrvl_nfc: Protect mrvl_nand_probe_dt ... Parsing DT nodes if CONFIG_OFTREE isn't enabled is pointless, also we should prefer potential platform_data passed earlier. Protect mrvl_nand_probe_dt by bailing out early if either CONFIG_OFTREE is not enabled or dev's platform_data is non-NULL. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	144adf2 Browse files » mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase ... Marvell NAND controller allows to enable an Auto Read Status feature that will automatically monitor NAND status during Erase and Program operations. Ready bit in status register will be set after the controller is sure the NAND device has finished the operation and saves us from guessing the real timeout values. Using the Auto Read Status feature prevents timeout issues on the two operations with none or wrong timing register setup. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	bb7a755 Browse files » mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00 ... If OOB data is not required on page program, we have to clear the corresponding data with 0xff instead of 0x00. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	774784c Browse files » mtd: nand_mrvl_nfc: Use common clock for core clock ... With PXA3xx now providing a common clock for the NAND clock, use it and get rid of the mach/clock.h. This will allow Marvell Armada 370/XP to reuse the same driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
	bcf9feb Browse files » mtd: nand: Clarify Marvell Orion Kconfig prompt ... Kconfig prompt for Marvell Orion SoCs is missing a "Marvell" prefix, add it to the prompt. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sebastian Hesselbarth authored on 20 Nov 2015 Sascha Hauer committed on 23 Nov 2015
2015-10-14	a5afa2d Browse files » mtd: nand_denali: don't include arch header ... It causes build failures on other arches than socfpga and the driver doesn't use anything provided by this header. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Lucas Stach authored on 14 Oct 2015 Sascha Hauer committed on 14 Oct 2015
2015-10-07	181bb31 Browse files » Merge branch 'for-next/mtd' Sascha Hauer committed on 7 Oct 2015
2015-09-23	16a6d8a Browse files » mtd denali: pass col argument to READID operation ... A read id operation followed by 0x00 reads the device ID while a read id operation followed by 0x20 reads the possible ONFI identifier. As the READID function did not propagate the second id parameter but had a hard-coded call for 0x90 0x00, reading the ONFI identifier was not possible and thus chips werde not detected (tested with MT29F8G08ABABAWP) Signed-off-by: Enrico Jorns <ejo@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Enrico Jorns authored on 21 Sep 2015 Sascha Hauer committed on 23 Sep 2015
	aca725c Browse files » mtd nand_denali: Add denali nand driver ... The driver is based on the denali driver from the linux kernel Signed-off-by: Enrico Jorns <ejo@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Enrico Jorns authored on 21 Sep 2015 Sascha Hauer committed on 23 Sep 2015
	61720f7 Browse files » mtd nand: added 'bits_per_cell' property ... This one is available in the kernel and used by the denali driver Signed-off-by: Enrico Jorns <ejo@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Enrico Jorns authored on 21 Sep 2015 Sascha Hauer committed on 23 Sep 2015
2015-09-02	1734538 Browse files » mtd: spi-nor: add Spansion S25FL204K support ... Spansion S25FL204K is a 4-Mbit 3.0V Serial Flash Memory with Uniform 4 kB Sectors. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 1 Sep 2015 Sascha Hauer committed on 2 Sep 2015
2015-09-01	60fc3e9 Browse files » Merge branch 'for-next/mtd' Sascha Hauer committed on 1 Sep 2015
2015-08-28	311f02f Browse files » mtd: spi-nor: mostly drop lock/unlock code ... The lock/unlock code is broken beyond repair. First of all the algorithm doesn't work properly. SPI NOR flashes can only protect a certain amount of blocks from the end of the device which is incompatible to the protect(start,len) API we have. The algorithm tries to be clever by doing protection only when it does not protect unrelated blocks and unprotection only when it does not unprotect unrelated blocks. This breaks for example when some code protects the last blocks (which may contain the bootloader), then protects the blocks before the last ones (which may contain the environment). Then if we try to overwrite the bootloader this won't work since it would unprotect the environment aswell, so the driver will not unprotect anything resulting in a failed erase/write later. Then the protection behaviour is different between different flashes. Some have three protection bits, some have four. For some the smallest protection are is 1/16 of the device, others have 1/256 or 1/64. Some have a bit which selects the lower area instead of upper area for protection. The position of this bit differs on different flashes. This patch removes the lock code completely and always unprotects the whole device. This way we can unprotect a device for writing to it and never protect it again. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 28 Aug 2015
2015-08-26	3e1adbf Browse files » mtd: m25p80: make it possible to use large blocks if desired ... Some SPI NOR flashes support 4K erase blocks. 4K erase blocks do not work with UBIFS which needs a minimum erase block size of 15360 bytes. Also bigger sectors are faster to erase. This patch adds a device tree option to use the bigger blocks instead of the default 4K blocks. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Sascha Hauer committed on 26 Aug 2015
2015-08-19	73deb9f Browse files » mtd: nand: mrvl-nand: create initial empty bbt ... When creating an initial bad blocks table, create it empty. This is necessary because when the bad block table blocks are not initialized (all ff) while some partitions are, all the blocks which have an OOB data not beginning with 0xff 0xff will be marked as bad blocks in the initial bad blocks scan. As a consequence, any existing blocks are impossible to erase anymore. Fix this by fixing the BBT creation flag. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Robert Jarzmik authored on 9 Aug 2015 Sascha Hauer committed on 19 Aug 2015
2015-08-19	81caed9 Browse files » spi-nor: Align spi_nor_ids[] with kernel 4.1 ... Sync the spi_nor_ids[] struct with the one from kernel 4.1. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Fabio Estevam authored on 15 Aug 2015 Sascha Hauer committed on 19 Aug 2015
2015-08-06	4ee01d2 Browse files » Merge branch 'for-next/misc' Sascha Hauer committed on 6 Aug 2015
2015-08-06	4f37af4 Browse files » mtd: nand_base: replace ifdef with IS_ENABLE ... Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 5 Aug 2015 Sascha Hauer committed on 6 Aug 2015