MIPS: ath79: dts: sync clk stuff with linux v4.7-rc2 ...

Please see these linux kernel ath79 commits:

    commit 1e6a349
    Author: Antony Pavlov <antonynpavlov@gmail.com>
    Date:   Thu Mar 17 06:34:17 2016 +0300

        MIPS: dts: qca: introduce AR9331 devicetree

    commit 5ae5c45
    Author: Antony Pavlov <antonynpavlov@gmail.com>
    Date:   Thu Mar 17 06:34:18 2016 +0300

        MIPS: ath79: update devicetree clock support for AR9331

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: ar933x: fix copyright header ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

driver: replace dev_request_mem_region with dev_request_mem_resource ...

dev_request_mem_region doesn't work properly one some SoCs on which
PTR_ERR() values clash with valid return values from dev_request_mem_region.
Replace them with dev_request_mem_resource where possible.

This patch has been generated with the following semantic patch:

// <smpl>
@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores)) {
...
-	return PTR_ERR(io);
-}
+	return PTR_ERR(iores);
+}
+io = IOMEM(iores->start);
...+>
}

@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores))
-	return PTR_ERR(io);
-}
+	return PTR_ERR(iores);
+io = IOMEM(iores->start);
...+>
}

@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
-	ret = PTR_ERR(io);
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores)) {
+	ret = PTR_ERR(iores);
...
}
+io = IOMEM(iores->start);
...+>
}

@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores))
+	return PTR_ERR(iores);
+io = IOMEM(iores->start);
...+>
}

@@
identifier func;
@@
func(...) {
<+...
struct resource *iores;
-struct resource *iores;
...+>
}
// </smpl>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

driver: Fix return check of dev_request_mem_region ...

dev_request_mem_region returns an ERR_PTR, fix places which check for a
NULL pointer instead. This patch has been generated with this semantic
patch, written by me and improved by Andrey Smirnov:

// <smpl>
@@
expression e;
expression e1;
@@
e = dev_request_mem_region(...);
...
-if (!e)
-	return e1;
+if (IS_ERR(e))
+	return PTR_ERR(e);

@ rule1 @
expression e;
@@
e = dev_request_mem_region(...);

@@
expression rule1.e;
identifier ret, label;
constant errno;
@@
if (!e) {
	...
(
-	ret = -errno;
+	ret = PTR_ERR(e);
	...
	goto label;
|
-	return -errno;
+	return PTR_ERR(e);
)
}

@depends on rule1@
expression rule1.e;
@@
-	if (e == NULL)
+	if (IS_ERR(e))
{
...
}
// </smpl>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

clk: mvebu: Add corediv clock driver for Armada 370/XP ...

Newer Marvell MVEBU SoC like Armada 370/XP have an additional core
clock divider for e.g. NAND clock. Add the corresponding driver based
on the Linux driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: socfpga: don't register fixed clocks ...

The fixed clocks are registered from devicetree. Therefore the code path is
not needed, but would instead register the clocks twice, which leads to the
error message:

	clk_register clk f2s_periph_ref_clk is already registered, skipping!
	of_clk_init: failed to init clock for /soc/clkmgr@ffd04000/clocks/f2s_periph_ref_clk: 1
	clk_register clk osc1 is already registered, skipping!
	of_clk_init: failed to init clock for /soc/clkmgr@ffd04000/clocks/osc1: 1

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: socfpga: fix dt binding support ...

Change the set_parent/get_parent functions for clock-gates to work
with the Linux kernel DT bindings.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX28: Add PWM clk support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: use 'const void *' for struct of_device_id.data ...

Since 2011 barebox' of_device_id struct uses unsigned long type for data field:

    struct of_device_id {
            char *compatible;
            unsigned long data;
    };

Almost always struct of_device_id.data field are used as pointer
and need 'unsigned long' casting.

E.g. see 'git grep -A 4 of_device_id drivers/' output:

    drivers/ata/sata-imx.c:static __maybe_unused struct of_device_id imx_sata_dt_ids[] = {
    drivers/ata/sata-imx.c- {
    drivers/ata/sata-imx.c-         .compatible = "fsl,imx6q-ahci",
    drivers/ata/sata-imx.c-         .data = (unsigned long)&data_imx6,
    drivers/ata/sata-imx.c- }, {

Here is of_device_id struct in linux kernel v4.0:

    struct of_device_id {
            char name[32];
            char type[32];
            char compatible[128];
            const void *data;
    };

Changing of_device_id.data type to 'const void *data' will increase
barebox' linux kernel compatibility and decrease number of 'unsigned
long' casts.

Part of the patch was done using the 'coccinelle' tool with the
following semantic patch:

    @rule1@
    identifier dev;
    identifier type;
    identifier func;
    @@
    func(...) {
    <...
    - dev_get_drvdata(dev, (unsigned long *)&type)
    + dev_get_drvdata(dev, (const void **)&type)
    ...>
    }
    @rule2@
    identifier dev;
    identifier type;
    identifier func;
    identifier data;
    @@
    func(...) {
    <...
    - dev_get_drvdata(dev, (unsigned long *)&type->data)
    + dev_get_drvdata(dev, (const void **)&type->data)
    ...>
    }

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: fractional-divider: fix build with CONFIG_MODULES ...

Fixes:
error: 'clk_register_fractional_divider' undeclared here

introduced with commit 22a0c31c9265 (CLK: Add fractional
divider clock support from Linux kernel)

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: clk-divider: fix _get_maxdiv for table based divider ...

The divider lacks the code for calculating the maximum divider for table
based dividers. Add it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/rockchip' ...

Conflicts:
	arch/arm/Kconfig

ARM: Rockchip: Update clk driver from Linux kernel for use with newer DTS ...

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: Treat NULL as dummy clocks ...

NULL pointers should be treated as dummy clocks as done in the kernel.
Using a not fully filled in clk * array for of_clk_add_provider may result
in NULL clks. When these are passed into the clk framework we should not
crash.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

CLK: Check and do not allow to register clock twice ...

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

CLK: clk-divider: Respect CLK_DIVIDER_POWER_OF_TWO flag ...

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

CLK: clk-divider: Introduce clk_divider_alloc() and *_free() routines ...

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

CLK: clk-divider: Respect CLK_DIVIDER_HIWORD_MASK flag ...

It is required for Rockchip SoCs where clock settings registers have
write-enable mask in high word.

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

CLK: clk-mux: Respect CLK_MUX_HIWORD_MASK flag ...

It is required for Rockchip SoCs where clock settings registers have
write-enable mask in high word.

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

CLK: Add fractional divider clock support from Linux kernel ...

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

CLK: Add support for composite clock from Linux kernel ...

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

drivers: remove unnecessary mach/imx-regs.h include ...

And replace the ones needed with the SoC specific header.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/tegra'

clk: tegra: don't enable UART clocks by default ...

Now that we are registering a proper driver for the
UARTs we no longer need to enable the clocks unconditionally.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: slow down MSELECT to 102MHz ...

Don't know where I got the 204MHZ previously, but
102MHz is the official supported maximum.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra124: add PCIe clocks ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra124: add PLLE setup functions ...

This adds functions to bring up the new style
Tegra114+ PLL_E.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: gate: remove superfluous code ...

This code didn't have any effect.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra30: add PCIe clocks ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: tegra: add PLLE setup functions ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>