net: e1000: don't try to register eeprom if MTD support is missing ...

EEPROM support is an optional feature and the driver should work
just fine without it.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: base: add chosen node if it does not exist when adding initrd ...

If the chosen node does not exist, of_add_initrd fails to pass the
initrd to the kernel. Instead it should create the chosen node, just
like of_fixup_bootargs does.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

spi: mvebu: fix baudrate selection for Armada 370/XP ...

There are two problems that made the driver choose the wrong baudrate
calculation algorithm:

a) The compatible used on 370/XP isn't marvell,armada-370-xp-spi but
   marvell,armada-370-spi or marvell,armada-xp-spi respectively.
b) The probe function uses
   	match = of_match_node(mvebu_spi_dt_ids, dev->device_node);
   to determine the right algorithm. As the devices are also compatible
   to marvell,orion-spi and this comes first in mvebu_spi_dt_ids[]
   it's always the older Orion algorithm that is used.

This patch fixes both problems.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/vybrid'

Merge branch 'for-next/state'

Merge branch 'for-next/socfpga'

Merge branch 'for-next/pci'

Merge branch 'for-next/net'

Merge branch 'for-next/mvebu'

Merge branch 'for-next/misc'

Merge branch 'for-next/imx'

clk: Port clock dependency resolution code ...

Port the clock dependency resolution algorithm utilized by Linux
kernel's version of of_clk_init(), to allow for SoCs whose DT clock
configuration reqires such behaviour for correct initialization (Vybrid
is one such example).

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: Add pinctrl driver for VF610 ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pinctrl: Add provisions to control GPIO pin direction ...

Some SoC (of which Vybrid is a one example) relegate GPIO direction
control to their pinmux IP block, instead of having that functionality
within GPIO IP. Add provisions to control that aspect of pinmux to
support such SoCs.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: of_find_path: Add support for new partition binding ...

The partitions now may be in a subnode of the actual device node.
Eventually go another step up in the hierarchy if required.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: partitions: Support new binding ...

The new binding recommends to put the partitions into a subnode
with compatible "fixed-partitions". Add support for this binding.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: add MX25U2033E ...

This chip can be found in 4th generation Kindle devices

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand: nand_mxs: Fix readtotal calculation ...

The calculation of readtotal must be bit alligend. If not the bch core
finds bit flips in every page, because readtotal is too small.
This bug was mostly introduced since commit "51061a9 mtd: nand: nand_mxs:
Add subpage read support".

Tested with:
nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion
S34ML08G2), 1024MiB, page size: 2048, OOB size: 128

nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron
MT29F4G08ABADAWP), 512MiB, page size: 2048, OOB size: 64

nand: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd3 (Samsung NAND
1GiB 3,3V 8-bit), 1024MiB, page size: 2048, OOB size: 64

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: Make UBI detection more robust ...

When we want to detect if a mtd device contains an UBI image then
testing the first block is not enough since it can always happen that
UBI has just erased the block before the power failed during last boot.
Since UBI only ever erases one block at a time and directly writes the
ec header to it afterwards, it shouldn't be necessary to scan the whole
device for UBI data. Scan the first 64 blocks. The first non-empty block
then must contain UBI data, if instead we find foreign data we assume
that no UBI is on that mtd device.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

nand: imx6: Changed default NAND clock ...

The Barebox recognized false bad erase blocks while booting from a
Spansion NAND (1). This error occurred due a to high clock. The
Kernel sets the default NAND clock to 22Mhz. So, to fix this error and
to be more identical with the Kernel, the Barebox should be too.

1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion
S34ML08G2), 1024MiB, page size: 2048, OOB size: 128

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net/designware: add explicit reset of {tx|rx}_currdescnum ...

Driver "init" function might be called multiple times.
On every "init" Tx/Rx buffer descriptors are initialized: "descs_init"
-> "{tx|rx}_descs_init".

In its turn those init functions set MAC's "{tx|rx}desclistaddr" to
point on the first buffer descriptor in the list.

So CPU to start operation from the first buffer descriptor as well after
every "init" we have to reset "{tx|rx}_currdescnum".

[Original U-Boot patch by Alexey Brodkin <abrodkin@synopsys.com>]

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: Respect "bus mode" register contents on SW reset ...

"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.

[Original U-Boot patch by Alexey Brodkin <abrodkin@synopsys.com>]

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net/designware: Do not select MIIPORT for RGMII interface ...

Do not select MIIPORT for RGMII interface

[Original U-Boot patch by Vipin Kumar <vipin.kumar@st.com>]

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net/designware: Consecutive writes to the same register to be avoided ...

There are a few registers where consecutive writes to the same location
should be avoided or have a delay.

According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:

DMA Registers:
Register 0        Bit 7
Register 6        All bits except for 24, 16-13, 2-1.

GMAC Registers:
Registers 0-3     All bits
Registers 6-7     All bits
Register 10       All bits
Register 11       All bits except for 5-6.
Registers 16-47   All bits
Register 48       All bits except for 18-16, 14.
Register 448      Bit 4.
Register 459      Bits 0-3.

[Original U-Boot patch by Dinh Nguyen <dinguyen@altera.com>]

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: add clock command completion ...

This adds tab completion for the clk_* commands.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: i.MX: Add i.MX6ul support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pinmux: imx-iomux-v3: Add i.MX6ul support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: phy: micrel: Do not overwrite reserved bits ...

ksz8021_config_init() unconditionally sets the KSZPHY_OMSO_RMII_OVERRIDE
bit. This is since the initial micrel phy commit, so it's not
reproducible where this comes from and why this is done. Neither U-Boot
nor the kernel ever touch this bit and so should we. Also, instead
of doing a write only operation, read/modify/write the bit we actually
want to change.
This fixes operation on a KSZ8081MLX which is a MII only phy.
KSZPHY_OMSO_RMII_OVERRIDE is reserved here and must be written to 0.
KSZPHY_OMSO_MII_OVERRIDE is default 1 and must be written as 1.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

watchdog: add designware driver ...

Port the linux v4.8-rc1 Synopsys DesignWare watchdog driver to barebox.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: split PCI hierarchy enumeration and config from device registration ...

This gets rid of some of the special cases in the bus scanning function
by splitting hierarchy enumeration and configuration and the actual
device registration into 2 passes.

This ensures that the PCI hierarchy below a root port is completely
set up before any device driver is probed.

This simplifies the code and makes it less error prone, while moving
the PCI address space layout closer to the one used by Linux.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>