ARM: imx233-olinuxino: add CONFIG_CONSOLE_ACTIVATE_ALL ...

if not set, barebox will use first console by default.
On this board first console is KEYBOARD_GPIO, so we will end
in unusable state.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: execute DMB before trying to flush cache ...

The CPU write buffer needs to be coherent with the cache, otherwise
we might flush stale entries with the actual data stuck in the cache.

This is really important on newer CPU core with bigger write buffers.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: correctly identify ARMv6 K/Z ...

The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other parts
(including the cache handling) is still at v6. As we don't make use of
the more advanced features of the v7 MMU in Barebox, it's okay to just
override this to properly identify the CPU as ARMv6.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: align exception vectors to 32 byte ...

On ARMv7 the exception vectors inside the barebox binary are used directly
by remapping the vectors base through the VBAR register. While VBAR allows
to remap the exception vectors freely, it still imposes a minimum alignment
of 32 byte, as the lower bits are treated as the exception vector offset.
Enforce this alignment inside the barebox binary.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX50: do not pass base address to imx53_boot_save_loc ...

This is a follow-up on commit cf3dfafff4cb.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/imx'

Merge branch 'for-next/efi'

ARM: i.MX7: Add PSCI support ...

This adds the SoC specific PSCI bits for i.MX7. Based on the
corresponding U-Boot code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add PSCI support ...

This patch contains the barebox implementation for the ARM
"Power State Coordination Interface" (PSCI).

The interface is aimed at the generalization of code in the following
power management scenarios:
* Core idle management.
* Dynamic addition and removal of cores, and secondary core boot.
* big.LITTLE migration.
* System shutdown and reset.

In practice, all that's currently implemented is a way to enable the
secondary core one some SoCs.

With PSCI the Kernel is either started in nonsecure or in Hypervisor
mode and PSCI is used to apply power to the secondary cores.

The start mode is passed in the global.bootm.secure_state variable. This
enum can contain "secure" (Kernel is started in secure mode, means no
PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available)
or "hyp" (Kernel is started in hyp mode, meaning it can support
virtualization).

We currently only support putting the secure monitor code into SDRAM,
which means we always steal some amount of memory from the Kernel.
To keep things simple for now we simply keep the whole barebox binary in
memory

The PSCI support has been tested on i.MX7 only so far. The only
supported operations are CPU_ON and CPU_OFF.

The PSCI and secure monitor code is based on the corresponding U-Boot
code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

config: Set UART port 2 as debug port ...

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: phycore-rk3288: Use UART2 as debug output ...

RK3288's UART2 is the default debug uart interface.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: start: Fix image size calculation ...

In barebox_non_pbl_start() we do not run at the address we are linked
at, so we must read linker variables using ld_var(). Since ld_var()
current is not available on arm64 we create two zero sized arrays,
one at the begin of the image and one at the end. The difference
between both is the image size we are looking for.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add smc call support ...

Taken from the Kernel: A wrapper to make a smc call from C.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add UNWIND macro ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: vf610: Add support for ZII VF610 Dev Family ...

Add support for ZII VF610 Dev based designs such as:

    - VF610 Dev, revision B
    - VF610 Dev, revision C
    - CFU1, revision A
    - SPU3, revision A
    - SCU4 AIB, revision C

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: Initialize CSU ...

The CSU needs to be initialized, otherwise we cannot access memory
in non secure mode.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: Add imx7s.dtsi ...

Needed for compiling the i.MX7 warp board which already includes this
file.

This file is necessary because the upstream dtsi file currently assigns
MX7D_CLK_DUMMY to the gpt1 clock we use, so we won't get a meaningful
clock rate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pinctrl: i.MX7: Fix LPSR sel_imput setting ...

The i.MX7 has two pinmux controllers, the regular and the LPSR
controller. The LPSR pinmux controller doesn't have any sel_input
registers, instead they can be found in the regular pinmux controller.
This means whenever we want to apply the the sel_input setting for
the LPSR controller, we have to apply them to the regular controller
instead.
In barebox take the easy way out and just add the difference of the
two base addresses to the register offset. The same issue is present
in the Kernel aswell, but when the bootloader already configured
the pins correctly nobody notices when the Kernel sel_input setup
effectively is a no-op.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: start: Fix boarddata allocation ...

It's essential that we always pass the same size value to
arm_mem_barebox_image(), otherwise the result will be inconsistent.
Pass arm_barebox_size instead of barebox_image_size as the latter
does not contain the max bss segment size.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX: Add i.MX6SL support ...

Most i.MX6SL infrastructure is already covered in barebox by general i.MX6
support. Missing infrastructure provided in separate commits are
* SoC type detection
* Clock infrastructure

Add the missing fsl,imx6sl-mmdc, so it will not be catched by fsl,imx6q-mmdc
and the remaining bits and pieces to provide barebox i.MX6SL SoC support.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX: add SoC type detection for i.MX6SL ...

The i.MX6 series SoC type is determined by barebox by examining the
USB_ANALOG_DIGPROG aka IMX6_ANATOP_SI_REV register. This register is located
at a common offset for all mx6 SoC - except for i.MX6SL where a different
offset is used. This creates a dilemma while distinguishing the mx6sl from
non-mx6sl SOC since the SoC type identification register location is type
specific itself.

Access to undocumented and probably invalid or unpredictable registers should
be avoided as possible. For the mx6sl detection an access to the general
USB_ANALOG_DIGPROG @0x260 cannot be avoided when running on mx6sl. This
register contained the value 0x00014009 for different mx6sl Rev. 1.2 based
e-book readers using MCIMX6L7DVN10AB and MCIMX6L8DVN10AB SoC. This
implementation assumes the value of MAJOR_UPPER (here 0x01) to be smaller
than the smallest non-6sl MAJOR_UPPER (0x61 for mx6s).

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX: move cpu_type macros in front of cpu_revision code ...

Preparational commit to enable the use of cpu_type macros in imx6_cpu_revision()

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: add AIPS base address defines ...

Import the ARM IP bus base addresses from IMX7DRM 05/2016 AIPS Memory Map

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT ...

This patch is based on a patch from the U-Boot and fixes two errors with
the LCDC. Original commit message from Jyri Sarha [1]:
"Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock."

The register values are generated by testing, because there is no formula
to calculate them. Also from Jyri Sarha [1]:
"In practice the only rule to find an optimal value is to find as high as
possible REG_PR_OLD_COUNT value that does not produce LCDC FIFO
underflows under worst case scenario. The worst case happens when the
highest pixel clock videomode with maximum bpp is used while memory
subsystem is stressed by endless stream of writes hitting the same
memory memory bank (can be the same address)."

It only contains the BeagleBone Black and the Phytec SoM, because I
don't have other boards.

[1] https://patchwork.ozlabs.org/patch/704013/

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: Kconfig: ARCH_IMX7 selects COMMON_CLK_OF_PROVIDER ...

Build of clk-imx7 depends on selection of COMMON_CLK_OF_PROVIDER

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

efi: don't unload drivers ...

EFI applications should be unloaded to avoid leaking memory. However, boot
or runtime services continue in the background. So they must not be
unloaded.

Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

efi: include and execute exit calls ...

Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: vf610-twr: remove unused variable ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: initialize architected timer ...

This is the same that U-Boot does. The registers are not documented.
Without this the architected timer on the i.MX7 does not work.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: Add WaRP7 board support ...

Signed-off-by Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>