ARM: interrupts64: Include ESR value in exception traceback ...

Oftentimes knowing the class of exception is not enough and full ESR
value is needed to decode the specifics. Add code to print ESR as a
part of excpetion traceback to provide that information.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: Make use of dsb() and isb() helpers ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: no-mmu: Disable building for ARMv8 ...

Disable building for ARMv8 since no-mmu.c only supports ARMv7

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu64: Convert flags in arch_remap_range() ...

Flags passed to arch_remap_range() are architecture independent, so it
can't be passed as is to map_region(). Add code to do the proper
conversion to avoid subtle bugs that this confusion brings.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu64: Make use of create_table() ...

Make use of create_table() instead of calling xmemalign() and memset()
explicitly.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu64: Trivial code simplification ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add i.MX8 support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[andrew.smirnov@gmail.com: fix B0 chips to report IMX_CHIP_REV_2_0]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: compile arm32 specific errata only for CPU32 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: xload: Fix compiler warning ...

the ESDHC controller is a 32bit device, so can do DMA only on the
lower 32bit. Fix the compiler warning about casting a pointer to integer
of different size on aarch64 by casting to unsigned long first. Error
out if the destination does not fit into 32bit though.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6sx: use correct clocks for GPT ...

This is a stop gap solution until the upstream DT is fixed. In Linux this isn't
an issue as the driver prefers the "osc_per" clock, falling back to "per" and
then doing different things based on the SoC type and if the input clock rate
matches 3MHz. As this isn't really how the hardware works, but a fragile mix of
the clock driver exposing a clock with a faked frequency and system knowledge in
the GPT driver I prefer not to replicate this horrors in the Barebox driver,
but instead just use the system clock source.

Fixes: 2ebda864f837
       (ARM: imx: clocksource: Use per clock for determining parent freq)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX50: fix Kindle-MX50 DT issues and warnings ...

Fix warnings generated from the kindle-mx50 dts when used in linux with W=1:
unit names should not have leading "0x"; reg property given, but no unit name;
use stdout-path instead of linux,stdout-path.
Also move the regulator-fixed node to the root node to match the convention.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

kwbimage_v0: add support to detect and boot a mvebu v0 image ...

The differences between v0 and v1 of the mvebu kwbimage are small enough
that the function to boot such an image can be shared between both
variants.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: ocotp: Move OCOTP driver to drivers/nvmem ...

Move OCOTP driver to drivers/nvmem to be consistent with Linux
kerenel.

Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Tested-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: ocotp: Simplify BF macro ...

Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Tested-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: ocotp: Simplify OCOTP field packing/unpacking ...

Simplify OCOTP field packing/unpacking with macros from
<linux/bitfield.h>.

Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Tested-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: ocotp: Change MAC address layout for VFxxx ...

For reasons unclear VFxxx port of U-Boot chose to store MAC address in
OCOTP using a layout that is incompatible with rest of i.MX
world (both in U-Boot and Barebox). Unfortunately for us, that means
that there are a number of boards out there that have had their MAC
addresses programmed using U-Boot and in order to properly support
those boards we need to change VFxxx port of Barebox to be compatible.

Since the number of Barebox users on VFxx is in single digits, just
chage the layout to that of U-Boot without trying to make this a
configurable option.

Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Tested-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: ocotp: Unify code paths for reading MAC address ...

There is no reason why code handling MAC-address properties of
"ocotp0" and code fetching this information to pass it along to
networking subsystem couldn't share majority of their code. Convert
the driver to do that.

Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Tested-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dove: fix bit layout of DOVE_CPU_CTRL register ...

While creating the previous patch I checked the cpu's reference manual
to see what the affected registers actually do and noticed that bits
of the DOVE_CPU_CTRL actually used by the code doesn't match the bits
described as AHBSlaveBase in the manual.

I'm not aware of any effect (neither positive nor negative) of this
patch.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dove: move memory controller remapping before RAM detection ...

Compared to other mvebu cpus the memory controller registers are in
their own register window that can be moved independently of the mbus
register window.

Since commit f05c6e095cf8 the available RAM configured by the boot ROM
is read out earlier. This happens to be before the memory controller
register window is moved and so dove_memory_find() fails. To fix this
move the memory controller window together with the mbus window.

This change allows to boot barebox first stage again on a Solidrun
Cubox.

Fixes: f05c6e095cf8 ("mvebu: rework how memory is detected")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: only create flat mapping when early MMU hasn't done it already ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: don't use optimized string functions for MIPS64 ...

Barebox port of optimized string functions from Linux lacks support for MIPS64.

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: 64BIT selects PHYS_ADDR_T_64BIT ...

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: add PHYS_ADDR_T_64BIT option ...

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: use CKSEG1 instead of KSEG1 ...

KSEG1 constant is defined for 32 bit MIPS only. Use CKSEG1 which is defined for
both MIPS32 and MIPS64.

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: fix copy_to_link_location for 64 bit mode ...

MIPS `lw` instruction loads a 32 bit word from memory on both 32 bit and 64 bit
systems. On the other hand LONGSIZE is either 4 or 8 depending on selected code
model. This discrepancy causes copy_to_link_location failure on 64 bit systems.

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: add proper IOMEM() declaration for MIPS64 ...

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

include/common.h: move IOMEM declaration for MIPS to arch/mips/include/asm/io.h ...

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: import 64-bit address conversion macros ...

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: Introduce ARM_TTB_SIZE ...

Commit 1c33aac ("ARM: use memalign to
allocate page table"), reasonalby changed TTB allocation size from
SZ_32K to SZ_16K (TTB's real size), but it also changed alignment from
SZ_16K to SZ_64K for unclear reasons.

Reading various TTBR related ARM documentation it seems that worst
case alignment for it is 16KiB (bits [0, 13 - N] must be zero) which
also matches early TTB allocation code.

Since both early and regular MMU code has to share this paramter,
introduce ARM_TTB_SIZE and use it in both cases for both size and
alignment.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: Implement on-demand PTE allocation ...

Allocating PTEs for every 4K page corresponding to SDRAM upfront costs
us quite a bit of memory: 1KB per 1MB or RAM. This is far from being a
deal-breaker for majority of use-cases, but for builds where amount of
free memory is in hundres of KBs* it becomes a real hurdle for being
able to use MMU (which also means no L1 cache).

Given how we really only need PTEs for a very few regions of memory
dedicated from DMA buffers (Ethernet, USB, etc), changing MMU code to
do on-demand section splitting can allow us to save significant amount
of memory without any functionality loss.

Below is a very trivial comparison of memory usages on start before
and after this patch is applied.

Before:

barebox@ZII VF610 Development Board, Rev B:/ meminfo
used: 1271584
free: 265553032

After:

barebox@ZII VF610 Development Board, Rev B:/ meminfo
used: 795276
free: 266024448

Tested on:

       - VF610 Tower Board,
       - VF610 ZII Development Board (Rev. C)
       - i.MX51 Babbage Board
       - i.MX7 SabreSD Board
       - i.MX6 ZII RDU2 Board
        - AT91SAM9X5-EK Board

* One example of such use-case is memory testing while running purely
  out of SRAM

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>