LuminaSensum/barebox

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History for barebox / arch

2018-08-08	f9fc825 Browse files » ARM: Mark SP as being clobbered in arm_setup_stack() ... Not sure why it was working before, but with recent update of AArch64 GCC to 8.1.1 on my Fedora 28 machine, compiling barebox_arm_entry() yields the following assembly: 0000000000002aac <barebox_arm_entry>: 2aac: a9bd7bfd stp x29, x30, [sp, #-48]! 2ab0: d1404023 sub x3, x1, #0x10, lsl #12 2ab4: d1004063 sub x3, x3, #0x10 2ab8: 910003fd mov x29, sp 2abc: 8b000063 add x3, x3, x0 2ac0: a90153f3 stp x19, x20, [sp, #16] 2ac4: aa0003f3 mov x19, x0 2ac8: aa0103f4 mov x20, x1 2acc: f90017e2 str x2, [sp, #40] <-- storing 'boarddata' on old stack 2ad0: 9100007f mov sp, x3 <-- setting up new stack 2ad4: 97ffffdd bl 2a48 <arm_early_mmu_cache_invalidate> 2ad8: f94017e2 ldr x2, [sp, #40] <--- sadness 2adc: aa1403e1 mov x1, x20 2ae0: aa1303e0 mov x0, x19 2ae4: 940000a1 bl 2d68 <barebox_multi_pbl_start> Which result in AArch64 image (i.MX8MQ) not being bootable. With SP marked as clobbered, the above assembly changes to the following: 0000000000002aac <barebox_arm_entry>: 2aac: a9bd7bfd stp x29, x30, [sp, #-48]! 2ab0: d1404023 sub x3, x1, #0x10, lsl #12 2ab4: d1004063 sub x3, x3, #0x10 2ab8: 910003fd mov x29, sp 2abc: a90153f3 stp x19, x20, [sp, #16] 2ac0: 8b000063 add x3, x3, x0 2ac4: aa0003f3 mov x19, x0 2ac8: aa0103f4 mov x20, x1 2acc: f90017a2 str x2, [x29, #40] 2ad0: 9100007f mov sp, x3 2ad4: 97ffffdd bl 2a48 <arm_early_mmu_cache_invalidate> 2ad8: f94017a2 ldr x2, [x29, #40] 2adc: aa1403e1 mov x1, x20 2ae0: aa1303e0 mov x0, x19 2ae4: 940000a1 bl 2d68 <barebox_multi_pbl_start> now x29 is used to access stored x2 which avoids the problem and allows the system to boot correctly. The change is a no-op on AArch32. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 7 Aug 2018 Sascha Hauer committed on 8 Aug 2018
	cc13a61 Browse files » ARM: phytec-som-am335x: make autoenable actually usable ... IS_ENABLED has to be passed the full symbol name including the CONFIG_ prefix. Otherwise IS_ENABLED evaluates to 0. Fixes: 2877e08f9e1a ("ARM: phytec-som-am335x: Add autoenable") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> -- Cc: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Uwe Kleine-König authored on 7 Aug 2018 Sascha Hauer committed on 8 Aug 2018
	6d1b29b Browse files » ARM: i.MX: fix compilation with BBU disabled ... Make a static inline wrapper actually static inline. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 8 Aug 2018
2018-07-27	7ba0f2d Browse files » ARM: mmu: fix cache flushing when replacing a section with a PTE ... When replacing a section with a PTE, we must make sure that the newly initialized PTE entries are flushed from the cache before changing the entry in the TTB. Otherwise a L1 TLB miss causes the hardware pagetable walker to walk into a PTE with undefined content, causing exactly that behaviour. Move all the necessary cache flushing to arm_create_pte(), to avoid any caller getting this wrong in the future. Fixes: e3e54c644180 (ARM: mmu: Implement on-demand PTE allocation) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Lucas Stach committed on 27 Jul 2018
2018-07-13	87c08ac Browse files » i.MX: iomuxv3: restore NO_PAD_CTRL semantic ... A NO_PAD_CTRL flag used to keep a pad configuration untouched. With commit 094820a63bfd ("i.MX: iomuxv3: Use helper functions in iomux-v3.h") the NO_PAD_CTRL semantic changed to set a pad configurations to zero, which breaks non-DT boards, where NO_PAD_CTRL is freqently used to keep a boot-up default pad configuration, which often is non zero. Restore the old semantic, dont write PAD_CTRL when NO_PAD_CTRL is set. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Alexander Kurz authored on 10 Jun 2018 Sascha Hauer committed on 13 Jul 2018
2018-07-12	7257e80 Browse files » ARM: MMU: fix arch_remap_range() across section boundaries ... Fixes: e3e54c6441 ARM: mmu: Implement on-demand PTE allocation PGD_FLAGS_WC_V7 lacks the PMD_TYPE_SECT and PMD_SECT_BUFFERABLE flags. Without them a dma_alloc_writecombine() creates an invalid section when it crosses a section boundary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Sascha Hauer committed on 12 Jul 2018
2018-07-09	49b5c5a Browse files » Merge branch 'for-next/vfxxx' Sascha Hauer committed on 9 Jul 2018
	7ad77a3 Browse files » Merge branch 'for-next/riscv' Sascha Hauer committed on 9 Jul 2018
	6af0422 Browse files » Merge branch 'for-next/misc' Sascha Hauer committed on 9 Jul 2018
	1f3af63 Browse files » Merge branch 'for-next/mips' Sascha Hauer committed on 9 Jul 2018
	64c7203 Browse files » Merge branch 'for-next/kill-oftree-f' ... Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 9 Jul 2018
	1073955 Browse files » Merge branch 'for-next/imx8mq' Sascha Hauer committed on 9 Jul 2018
	47d229d Browse files » Merge branch 'for-next/imx' Sascha Hauer committed on 9 Jul 2018
	0d0e894 Browse files » Merge branch 'for-next/dts-warnings' Sascha Hauer committed on 9 Jul 2018
	0e8bd85 Browse files » Merge branch 'for-next/bootm' Sascha Hauer committed on 9 Jul 2018
	b5ba232 Browse files » Merge branch 'for-next/arm' Sascha Hauer committed on 9 Jul 2018
2018-07-05	31f7b0f Browse files » ARM: dts: rdu2: Make use of "zii,eeprom-name" ... Convert RAVE SP EEPROMs to use "zii,eeprom-name" instead of aliases in order to minimize differences with upstream Linux DT. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 4 Jul 2018 Sascha Hauer committed on 5 Jul 2018
2018-07-05	8acdd69 Browse files » ARM: dts: rdu1: Make use of "zii,eeprom-name" ... Convert RAVE SP EEPROMs to use "zii,eeprom-name" instead of aliases in order to minimize differences with upstream Linux DT. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 4 Jul 2018 Sascha Hauer committed on 5 Jul 2018
2018-07-02	21d7093 Browse files » ARM: dts: rdu1: Add node for backlight device ... Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 29 Jun 2018 Sascha Hauer committed on 2 Jul 2018
	f733735 Browse files » ARM: dts: rdu1: Specify "boot-source" NVMEM cell ... Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 29 Jun 2018 Sascha Hauer committed on 2 Jul 2018
	99b1fc1 Browse files » ARM: dts: rdu1: Add nodes for RAVE SP EEPROM ... Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 29 Jun 2018 Sascha Hauer committed on 2 Jul 2018
	e15ee51 Browse files » ARM: i.MX: Add support for ZII RDU1 board ... ZII RDU1 is a i.MX51 based, Babbagde board derivative supported by upstream kernel. This commit add support for it to Barebox. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 28 Jun 2018 Sascha Hauer committed on 2 Jul 2018
	87515c9 Browse files » ARM: babbage: Make PMIC initialization shareable ... Some board designs copy i.MX51 Babbadge board's PMIC design and so require exactly the same initialization. Move correspoding code into a separate file so it can be shared. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Andrey Smirnov authored on 28 Jun 2018 Sascha Hauer committed on 2 Jul 2018
	29e9cd1 Browse files » ARM: i.MX: bbu: support partitions starting at i.MX header ... The i.MX header is at an offset in the boot device, usually 0x400 bytes. This patch adds a flag to support the case that the partition the image is written to starts at that offset rather than 0x0. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 2 Jul 2018
	2603414 Browse files » ARM: i.MX: bbu: reimplement IMX_INTERNAL_FLAG_KEEP_DOSPART flag ... This patch reimplements the IMX_INTERNAL_FLAG_KEEP_DOSPART flag and makes it more generic. Until now we only kept a dos partition table over the update. Beginning with i.MX8 we may also want to preserve a GPT, so we have to extend the preserved area. It might also be the case that not (only) a partition table is stored in the initial area of a device, but also other unrelated data, so it's better to just keep the initial area that is unused by the i.MX ROM. It's also good to export the flag to allow boards to specify the initial area shall be preserved. When a board wants to set the flag for a mtd like device then it has to check for suitable erase sizes beforehand. We do not check this (yet). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 2 Jul 2018
	0e7f667 Browse files » ARM: i.MX: bbu: remove handler specific flags variable ... Now that we can store flags in the generic handler flags we no longer need our own variable. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha Hauer committed on 2 Jul 2018
	26cab6f Browse files » arm: arria10: enable errata 794072 and 845369 ... Enable workarounds for two of the errata the CPU is affected with. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Oleksij Rempel authored on 29 Jun 2018 Sascha Hauer committed on 2 Jul 2018
	5500987 Browse files » MIPS: don't include generated header files into MIPS asm files ... This patch came out of discussions in the 'MIPS parallel build breakage' e-mail thread: http://lists.infradead.org/pipermail/barebox/2018-March/032251.html Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 29 Jun 2018 Sascha Hauer committed on 2 Jul 2018
2018-06-29	76ad005 Browse files » ARM: imx6qp: fix NoC QoS passthrough for new cpu type functions. ... On i.MX6QP/DP cpu_mx6_is_mx6q/d do not return true anymore. Use the new cpu_mx6_is_mx6qp/dp to reenable NoC regulator bypass. Fixes: d4c05d29d484 ("ARM: i.MX6: Add cpu type for 'plus' variants") Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Philipp Zabel authored on 28 Jun 2018 Sascha Hauer committed on 29 Jun 2018
2018-06-29	36c4247 Browse files » MIPS: Use generic GCC library routines from lib/ ... This is a port of Linux kernel commit \| commit `740129b` \| Author: Antony Pavlov <antonynpavlov@gmail.com> \| Date: Wed Apr 11 08:50:19 2018 +0100 \| \| MIPS: Use generic GCC library routines from lib/ Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Antony Pavlov authored on 28 Jun 2018 Sascha Hauer committed on 29 Jun 2018