clk: imx: sync imx8mq clock driver with upstream kernel ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: add imx8mq composite clock ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: add divider_recalc_rate helper ...

Closer to Linux kernel implementation and needed for imx8mq
composite clock.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: move struct clk_mux into header ...

To make it reusable in a composite clock.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: move struct clk_gate into header ...

To make it reusable in a composite clock.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx5: add di_pred ...

This was missing, so the default external DI clock source on i.MX51 was
missing. Also set the divider to a division ratio of 1 initially, to avoid
complicating the logic in the IPU driver further.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/missing-prototypes'

Merge branch 'for-next/imx'

Merge branch 'for-next/checkpatch'

clk: fix NULL deref without OF node in debug message ...

of_clk_add_provider() may be called for devices added via
add_generic_device(). There is no OF node in this case, leading to a crash
when debug logs are enabled.

This affects various i.MX CPUs, which add imx*-ccm clock devices using
add_generic_device().

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: cpu: avoid use after free on error ...

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX5 clock: add clock provider support ...

Currently it is impossible to get clks with clk_get(&clk, "name");
on the mx5 platform. Change that by adding clk-imx5 as clk_provider.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: Avoid missing prototype warnings ...

clk_gate2_free() is unused, so remove it. clk_gate2_alloc() is only
used locally, so make it static.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/missing-prototypes'

ARM: clk: rk3188: don't set same clk rate twice ...

We found setting a clock rate which has already been set, rk3188 (radxa rock
pro) bails out. This is a quick fix only. Underlying situation not (yet)
investigated: why it is even trying to set it to the same rate again. It
remains to state that some but not all rrpro boards exhibit this behaviour, no
other rk3188 boards have been tested.

Signed-off-by: P. Rachet <perachet7@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

drivers: clk: imx5: Make locally used functions static ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX8MQ: Add missing IMX8MQ_CLK_TMU_ROOT clock ...

Add missing IMX8MQ_CLK_TMU_ROOT clock needed for CPU thermal sensor.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX8MQ: Bump refcounters of various important clocks ...

Bump refcounters of various important clocks in order to make sure
their parents are not disabled during clock re-configuration added by
commits that follow.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX28: Add APBH clk support ...

i.MX28 fails to use DMA and NAND because it cannot find its clock.
Add the clock for APBH.

Fixes: 6eb2ba6f1b ("dma: apbh: Enable clock as a part of probing")

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: clk-sccg-pll: Remove leftover debug output ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/imx'

mtd: gpmi-nand: Make sure clock is disabled during rate change ...

On i.MX6 GPMI Nand controller the clock must be disabled during
a rate change. Otherwise glitches on the clock line may occur
which result in errors like:

MXS NAND: Error sending command
MXS NAND: DMA read error

There were previous attempts to fix this. One is in:

54961378f0 imx6: clk: Gate off ENFC clock before setting clock rate

This patch added a clk_disable() right before the rate change. Since
a clk_disable() on a disabled clk is a no-op, the patch added a
clk_enable() to the i.MX6 clk driver in the hope that the clk is
enabled in the nand driver probe and the clk_disable() really takes
place.

This patch doesn't work. First of all it enabled the enfc_podf clk
which was not the one that was actually disabled in the nand driver,
resulting in the nand drivers call to clk_disable() still being a
no-op. Then this patch also only works only on the classic i.MX6 which
was the only one supported at that time, but not on the i.MX6UL, i.MX6SX
and i.MX6SL which have a separate clk driver.

Instead of adding more quirks to the other i.MX6 clk drivers, fix this
in the GPMI driver. We no longer call clk_disable() on a disabled clk,
but instead do a clk_enable() first which makes sure the hardware state
is synchronized to the usage count and the following clk_disable()
is really effective. At the same time we can (and actually must) remove
the quirk in the i.MX6 clk driver.

Also add clk_disable()/clk_enable() around another rate change in the
GPMI driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: imx: remove unused clk_gate2_inverted ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v4.18-rc1 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/imx'

clock: Add i.MX8MQ clock driver ...

This is based on Lucas' patch sent as "[PATCH v2 4/4] clk: imx: add
clock driver for i.MX8MQ CCM" to the mailing list.

It will likely need some rework before it is finally merged, so apply
the reworks here before merging into barebox.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[andrew.smirnov@gmail.com: Fix pll type for IMX8MQ_VIDEO2_PLL1]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: support pinmux configuration in clock provider nodes ...

Some device trees use pinctrl-* settings inside device tree nodes for
clock providers.

Barebox does not threat clock providers (such as fixed-clock or
gpio-gate-clock) as conventional devices, thus setting default
pinctrl configuration in driver binding code does not happen for
clock providers.

This patch adds setting default pinctrl configuration to of_clk_init(),
just before calling clock provider's probe routine.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: add clk-gpio driver ...

This implements support for gpio-gate-clock device tree nodes, that
define clocks that can be enabled or disabled via GPIO line.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX6: Fix enfc_sel for i.MX6dqp ...

The plus SoC variants have some differences in the clock controller.
For now fix the NAND controller clock. There are more differences
that might be relevant, but for now are left for a future excercise.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX6: Adjust GPMI parent clock ...

Based on the corresponding Kernel code:

The gpmi needs 100MHz frequency in the EDO/Sync mode, We can not get the
100MHz from the pll2_pfd0_352m. So choose pll2_pfd2_396m as enfc_sel's
parent.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>