mfd: syscon: Switch to using %pa to print memory addresses ...

Switch to using %pa to print memory addresses in order to be able to
support both 64 and 32 bit builds.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

zynqmp: enable macb Ethernet support ...

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

macb: disable second priority queue for zynqmp gem support ...

Provide descriptors for second priority rx and tx queues and disable the
the queues if hardware is GEM. Otherwise the function macb_send() will run
into a timeout.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

macb: fix memory leakage due to double allocation of rx_buffer ...

Remove memory allocation of rx buffer in function
macb_init_rx_buffer_size, which caused a memory leak since it also is
alocated in macb_probe().

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

macb: fix check if hw is gem ...

Fix check for peripheral version in MACB_MID register to treat Xilinx
ZynqMP as GEM. All MIDs >= 2 indicate a GEM not only MID == 2.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

macb: fix format specifiers for debug output ...

Fixes compiler warning "format '%d' expects argument of type 'int', but
argument 4 has type 'size_t {aka long unsigned int}' [-Wformat=]".

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dp83867: port from linux ...

Port driver for TI DP83867 Gigabit Ethernet PHY from linux.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Constify dw_pcie_host_ops structures ...

Port of a Linux commit 4ab2e7c

  The dw_pcie_host_ops structures are never modified.  Constify these
  structures such that these can be write-protected.

  Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>
  Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Small computation improvement ...

Port of a Linux commit 6995de2

  Replace a division by 2 operation for a right shift rotation of 1 bit.

  Probably any recent and decent compiler does this kind of substitution
  in order to improve code performance. Nevertheless it's a coding good
  practice whenever there is a division / multiplication by multiple of 2
  to replace it by the equivalent operation in this case, the shift
  rotation.

  Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Fix enumeration end when reaching root subordinate ...

Port of a Linux commit c2deae4

  The subordinate value indicates the highest bus number which can be
  reached downstream though a certain device.

  Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
  parent")
  ensures that downstream devices cannot assign busnumbers higher than the
  upstream device subordinate number, which was indeed illogical.

  By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
  value of 0x01.

  Due to this combined with above commit, enumeration stops digging deeper
  downstream as soon as bus num 0x01 has been assigned, which is always
  the case for a bridge device.

  This results in all devices behind a bridge bus to remain undetected, as
  these would be connected to bus 0x02 or higher.

  Fix this by initializing the RC to a subordinate value of 0xff, which is
  not altering hardware behaviour in any way, but informs probing
  function pci_scan_bridge() later on which reads this value back from
  register.

  Following nasty errors during boot are also fixed by this:

  [    0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff]
  under [bus 01] (conflicts with (null) [bus 01])
  ...
  [    0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge
  0000:01 [bus 01]
  ...
  [    0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge
  0000:01 [bus 01]
  ...
  [    0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge
  0000:01 [bus 01]
  [    0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to
  05
  [    0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05]
  under [bus 01] (conflicts with (null) [bus 01])
  [    0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind
  bridge 0000:01 [bus 01]

  Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in
  parent")
  Tested-by: Niklas Cassel <niklas.cassel@axis.com>
  Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
  Tested-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
  Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
  Acked-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: <stable@vger.kernel.org> # 4.15
  Cc: Binghui Wang <wangbinghui@hisilicon.com>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Jesper Nilsson <jesper.nilsson@axis.com>
  Cc: Jianguo Sun <sunjianguo1@huawei.com>
  Cc: Jingoo Han <jingoohan1@gmail.com>
  Cc: Kishon Vijay Abraham I <kishon@ti.com>
  Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
  Cc: Minghuan Lian <minghuan.Lian@freescale.com>
  Cc: Mingkai Hu <mingkai.hu@freescale.com>
  Cc: Murali Karicheri <m-karicheri2@ti.com>
  Cc: Pratyush Anand <pratyush.anand@gmail.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>
  Cc: Roy Zang <tie-fei.zang@freescale.com>
  Cc: Shawn Guo <shawn.guo@linaro.org>
  Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
  Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  Cc: Xiaowei Song <songxiaowei@hisilicon.com>
  Cc: Zhou Wang <wangzhou1@hisilicon.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates ...

Port of a Linux commit d91dfe5

  dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt
  Pin registers, but the fixes don't actually work because these registers
  are read-only.

  Enable write permission before updating the Class Code and Interrupt
  Pin.

  Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Roy Zang <tie-fei.zang@freescale.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Add accessors for write permission of DBI ...

Port of a Linux commit e44abfe

  The read-only DBI registers can be written only when the "Write to RO
  Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set.

  Add accessors to enable and disable write permission, and use them instead
  of accessing MISC_CONTROL_1_OFF directly.

  Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Roy Zang <tie-fei.zang@freescale.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Handle ->host_init() failures ...

Port of a Linux commit 4a30176

  In several dwc-based drivers, ->host_init() can fail, so make sure to
  propagate and handle this to avoid continuing operation of a driver or
  hardware in an invalid state.

  Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Replace lower into upper case characters ...

Port of a Linux commit b4a8a51

  Replace of all initial lowercase character in comments and debug messages
  to uppercase to maintain coherence.

  Fix messages coherence within the DesignWare driver.

  Fix code style on dw_pcie_irq_domain_free() function.

  Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate ...

Port of a Linux commit 8cfab3c

  Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license.

  Remove the boilerplate GPL version 2 language, relying on the assertion in
  b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
  files with no license") that the SPDX identifier may be used instead of the
  full boilerplate text.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Fix typos and whitespace errors ...

Port of a Linux commit 96291d5

  Fix various typos and whitespace errors:

    s/Synopsis/Synopsys/
    s/Designware/DesignWare/
    s/Keystine/Keystone/
    s/gpio/GPIO/
    s/pcie/PCIe/
    s/phy/PHY/
    s/confgiruation/configuration/

  No functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static ...

Port of a Linux commit 684a3a9

  Helper functions dw_pcie_prog_*_atu_unroll() don't need to be in global
  scope, so make them static.

  Cleans up sparse warnings:
    - symbol 'dw_pcie_prog_outbound_atu_unroll' was not declared. Should it be static?
    - symbol 'dw_pcie_prog_inbound_atu_unroll' was not declared. Should it be static?

  Signed-off-by: Carlos Palminha <palminha@synopsys.com>
  [bhelgaas: rewrap to fit in 80 columns]
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically ...

Port of a Linux commit e9be4d7

  The ATU CTRL2 register is 32 bits, and bits other than the enable bit may
  be set.  To check whether the ATU is enabled or not, we should test the
  enable bit specifically.

  Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Joao Pinto <jpinto@synopsys.com>
  Acked-by: Jingoo Han <jingoohan1@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Move _unroll configurations to a separate function ...

Port of a Linux commit edd45e3

  No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to
  dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these
  functions are used to perform only outbound configurations. Also move
  these _unroll configurations to a separate function.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes ...

Port of a Linux commit a509d7d

  Previously dbi accessors can be used to access data of size 4 bytes. But
  there might be situations (like accessing MSI_MESSAGE_CONTROL in order to
  set/get the number of required MSI interrupts in EP mode) where dbi
  accessors must be used to access data of size 2. This is in preparation
  for adding endpoint mode support to designware driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Niklas Cassel <niklas.cassel@axis.com>
  Cc: Jingoo Han <jingoohan1@gmail.com>
  Cc: Joao Pinto <Joao.Pinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Modify dbi accessors to take dbi_base as argument ...

Port of a Linux commit b50b2db

  dwc has 2 dbi address space labeled dbics and dbics2. The existing helper
  to access dbi address space can access only dbics. However dbics2 has to
  be accessed for programming the BAR registers in the case of EP mode. This
  is in preparation for adding EP mode support to dwc driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Niklas Cassel <niklas.cassel@axis.com>
  Cc: Jingoo Han <jingoohan1@gmail.com>
  Cc: Joao Pinto <Joao.Pinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Split pcie-designware.c into host and core files ...

Port of a Linux commit feb85d9

  Split pcie-designware.c into pcie-designware-host.c that contains the host
  specific parts of the driver and pcie-designware.c that contains the parts
  used by both host driver and endpoint driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Fix style errors in pcie-designware.c ...

Port of a Linux commit 314fc85

  No functional change. Fix all checkpatch warnings and check errors in
  pcie-designware.c

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-By: Joao Pinto <jpinto@synopsys.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() ...

Port of a Linux commit 5f334db

  The "num-lanes" DT property is parsed in dw_pcie_host_init(). However
  num-lanes is applicable to both root complex mode and endpoint mode. As a
  first step, move the parsing of this property outside dw_pcie_host_init().
  This is in preparation for splitting pcie-designware.c to pcie-designware.c
  and pcie-designware-host.c

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: all: Split struct pcie_port into host-only and core structures ...

Port of a Linux commit 442ec4c

  Keep only the host-specific members in struct pcie_port and move the common
  members (i.e common to both host and endpoint) to struct dw_pcie.  This is
  in preparation for adding endpoint mode support to designware driver.

  While at that also fix checkpatch warnings.

  Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  CC: Jingoo Han <jingoohan1@gmail.com>
  CC: Richard Zhu <hongxing.zhu@nxp.com>
  CC: Lucas Stach <l.stach@pengutronix.de>
  CC: Murali Karicheri <m-karicheri2@ti.com>
  CC: Minghuan Lian <minghuan.Lian@freescale.com>
  CC: Mingkai Hu <mingkai.hu@freescale.com>
  CC: Roy Zang <tie-fei.zang@freescale.com>
  CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  CC: Niklas Cassel <niklas.cassel@axis.com>
  CC: Jesper Nilsson <jesper.nilsson@axis.com>
  CC: Joao Pinto <Joao.Pinto@synopsys.com>
  CC: Zhou Wang <wangzhou1@hisilicon.com>
  CC: Gabriele Paoloni <gabriele.paoloni@huawei.com>
  CC: Stanimir Varbanov <svarbanov@mm-sol.com>
  CC: Pratyush Anand <pratyush.anand@gmail.com>

For convenience sake, commit c046406

  PCI: dwc: Fix crashes seen due to missing assignments

  Fix the following crash, seen in dwc/pci-imx6.

    Unable to handle kernel NULL pointer dereference at virtual address 00000070
    pgd = c0004000
    [00000070] *pgd=00000000
    Internal error: Oops: 805 [#1] SMP ARM
    Modules linked in:
    CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.10.0-09686-g9e31489 #1
    Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
    task: cb850000 task.stack: cb84e000
    PC is at imx6_pcie_probe+0x2f4/0x414
    ...

  While at it, fix the same problem in various drivers instead of waiting for
  individual crash reports.

  The change in the imx6 driver was tested with qemu. The changes in other
  drivers are based on code inspection and have been compile tested only.

  Fixes: 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures")
  Signed-off-by: Guenter Roeck <linux@roeck-us.net>
  Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>  # designware-plat
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

was squashed into this one as well.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Remove LTSSM disable workaround ...

Port of a Linux commit a712807

  This causes CPU hangs when the system is reset by the watchdog, as the GPRs
  aren't cleared, but the clocks are back to disabled state.

  If the bootloader uses PCIe, it must take care to bring it down into a safe
  state, before passing control to the Linux kernel.  This is the only way to
  get a properly operating system at all times and circumstances.

  Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

LTSSM disable workaround still needs to be performed before passing
control to Linux. However, in order to avoid the hang described above,
we move it to imx6_pcie_remove() and apply it without relying on
values in GPR.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Remove redundant "Link never came up" message ...

Port of a Linux commit caf3f56

  When a PCI card is not connected, the following messages are seen on mx6:

    imx6q-pcie 1ffc000.pcie: phy link never came up
    imx6q-pcie 1ffc000.pcie: Link never came up

  The first one comes from the pcie-designware.c core file, so remove
  the redundant one from the imx6 driver.

  Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Add DT property for link gen, default to Gen1 ...

Port of a Linux commit a5fcec4

  Freescale has stated [1] that the LVDS clock source of the IMX6 does not
  pass the PCI Gen2 clock jitter test, therefore unless an external Gen2
  compliant external clock source is present and supplied back to the IMX6
  PCIe core via LVDS CLK1/CLK2 you can not claim Gen2 compliance.

  Add a DT property to specify Gen1 vs Gen2 and check this before allowing a
  Gen2 link.

  We default to Gen1 if the property is not present because at this time
  there are no IMX6 boards in mainline that 'input' a clock on LVDS
  CLK1/CLK2.

  In order to be Gen2 compliant on IMX6 you need to:

   - Have a Gen2 compliant external clock generator and route that clock back
     to either LVDS CLK1 or LVDS CLK2 as an input (see IMX6SX-SabreSD
     reference design).

   - Specify this clock in the PCIe node in the DT (i.e.,
     IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of
     IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output).

  [1] https://community.freescale.com/message/453209

  Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  CC: Fabio Estevam <fabio.estevam@freescale.com>
  CC: Zhu Richard <Richard.Zhu@freescale.com>
  CC: Akshay Bhat <akshay.bhat@timesys.com>
  CC: Rob Herring <robh+dt@kernel.org>
  CC: Shawn Guo <shawnguo@kernel.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Factor out ref clock enable ...

Port of a Linux commit 4d1821e

  Factor out ref clock enable to make it cleaner to add imx6sx support.  No
  functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Tested-by: Christoph Fritz <chf.fritz@googlemail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Remove unused return values ...

Port of a Linux commit 9ab021b

  Remove unused return values.  No functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>